Inventor · disambiguated record
Raguram Damodaran
Also filed as: DAMODARAN RAGURAM
61 granted patents·9 pending applications·412 citations·filing 2000–2020
98Inventor score
Files withTEXAS INSTRUMENTS INC29QUALCOMM INC16DAMODARAN RAGURAM13CHACHAD ABHIJEET ASHOK6TRAN JONATHAN SON HUNG2
Top patents by PatentIndex Score
70 records- 0197US6594713B1Hub interface unit and application unit interfaces for expanded direct memory access processorTEXAS INSTRUMENTS INC·Filed 2000·Granted Jul 15, 2003·200 cites·27 claims
- 0296US10108417B2Storing narrow produced values for instruction operands directly in a register map in an out-of-order processorQUALCOMM INC·Filed 2015·Granted Oct 23, 2018·42 cites·30 claims
- 0394US9298643B2Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirtyTEXAS INSTRUMENTS INC·Filed 2015·Granted Mar 29, 2016·7 cites·4 claims
- 0493US8732416B2Requester based transaction status reporting in a system with multi-level memoryDAMODARAN RAGURAM·Filed 2011·Granted May 20, 2014·7 cites·13 claims
- 0590US9244837B2Zero cycle clock invalidate operationTEXAS INSTRUMENTS INC·Filed 2012·Granted Jan 26, 2016·12 cites·5 claims
- 0689US10713180B2Lookahead priority collection to support priority elevationTEXAS INSTRUMENTS INC·Filed 2018·Granted Jul 14, 2020·2 cites·16 claims
- 0789US9830152B2Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processorQUALCOMM INC·Filed 2015·Granted Nov 28, 2017·8 cites·30 claims
- 0889US9268708B2Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherenceTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 23, 2016·3 cites·2 claims
- 0988US9009408B2Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache systemCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Apr 14, 2015·5 cites·4 claims
- 1087US10089114B2Multiple instruction issuance with parallel inter-group and intra-group pickingQUALCOMM INC·Filed 2016·Granted Oct 2, 2018·7 cites·31 claims
- 1187US8904115B2Cache with multiple access pipelinesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Dec 2, 2014·4 cites·2 claims
- 1285US8201004B2Entry/exit control to/from a low power state in a complex multi level memory systemANDERSON TIMOTHY DAVID·Filed 2007·Granted Jun 12, 2012·13 cites·8 claims
- 1383US8656105B2Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfersDAMODARAN RAGURAM·Filed 2011·Granted Feb 18, 2014·2 cites·12 claims
- 1482US7325178B2Programmable built in self test of memoryTEXAS INSTRUMENTS INC·Filed 2004·Granted Jan 29, 2008·30 cites·5 claims
- 1580US9575901B2Programmable address-based write-through cache controlTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 21, 2017·1 cites·3 claims
- 1680US8707127B2Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routinesTRAN JONATHAN SON HUNG·Filed 2011·Granted Apr 22, 2014·2 cites·4 claims
- 1778US8560896B2Priority based exception mechanism for multi-level cache controllerZBICIAK JOSEPH RAYMOND MICHAEL·Filed 2011·Granted Oct 15, 2013·2 cites·5 claims
- 1877US9183084B2Memory attribute sharing between differing cache levels of multilevel cacheDAMODARAN RAGURAM·Filed 2011·Granted Nov 10, 2015·1 cites·6 claims
- 1976US11537532B2Lookahead priority collection to support priority elevationTEXAS INSTRUMENTS INC·Filed 2020·Granted Dec 27, 2022·0 cites·20 claims
- 2075US11709679B2Providing load address predictions using address prediction tables based on load path history in processor-based systemsQUALCOMM INC·Filed 2016·Granted Jul 25, 2023·2 cites·23 claims
- 2174US8977821B2Parallel processing of multiple block coherence operationsTEXAS INSTRUMENTS INC·Filed 2012·Granted Mar 10, 2015·3 cites·5 claims
- 2272US7240277B2Memory error detection reportingTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 3, 2007·19 cites·16 claims
- 2371US7277808B1Process parameter based I/O timing programmability using electrical fuse elementsTEXAS INSTRUMENTS INC·Filed 2006·Granted Oct 2, 2007·6 cites·9 claims
- 2468US9851774B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2016·Granted Dec 26, 2017·1 cites·29 claims
- 2567US10474462B2Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructionsQUALCOMM INC·Filed 2016·Granted Nov 12, 2019·1 cites·30 claims
- 2667US7158902B2Process parameter based I/O timing programmability using electrical fuse elementsTEXAS INSTRUMENTS INC·Filed 2003·Granted Jan 2, 2007·13 cites·11 claims
- 2764US8598932B2Integer and half clock step division digital variable clock dividerTEXAS INSTRUMENTS INC·Filed 2013·Granted Dec 3, 2013·0 cites·4 claims
- 2864US7475313B2Unique pBIST features for advanced memory testingTEXAS INSTRUMENTS INC·Filed 2006·Granted Jan 6, 2009·5 cites·8 claims
- 2962US9195610B2Transaction info bypass for nodes coupled to an interconnect fabricBALASUBRAMANIAN DHEERA·Filed 2011·Granted Nov 24, 2015·0 cites·28 claims
- 3061US9189331B2Programmable address-based write-through cache controlDAMODARAN RAGURAM·Filed 2011·Granted Nov 17, 2015·0 cites·3 claims
- 3161US9003122B2Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherenceDAMODARAN RAGURAM·Filed 2011·Granted Apr 7, 2015·0 cites·2 claims
- 3260US8904110B2Distributed user controlled multilevel block and global cache coherence with accurate completion statusDAMODARAN RAGURAM·Filed 2011·Granted Dec 2, 2014·0 cites·13 claims
- 3360US8732398B2Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performanceCHACHAD ABHIJEET ASHOK·Filed 2011·Granted May 20, 2014·0 cites·16 claims
- 3460US7603487B2Hardware configurable hub interface unitTEXAS INSTRUMENTS INC·Filed 2005·Granted Oct 13, 2009·3 cites·14 claims
- 3559US9075743B2Managing bandwidth allocation in a processing node using distributed arbitrationDAMODARAN RAGURAM·Filed 2011·Granted Jul 7, 2015·0 cites·12 claims
- 3659US7324392B2ROM-based memory testingTEXAS INSTRUMENTS INC·Filed 2006·Granted Jan 29, 2008·5 cites·5 claims
- 3758US8856446B2Hazard prevention for data conflicts between level one data cache line allocates and snoop writesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Oct 7, 2014·0 cites·3 claims
- 3857US10551896B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2017·Granted Feb 4, 2020·0 cites·36 claims
- 3957US8532247B2Integer and half clock step division digital variable clock dividerVENKATASUBRAMANIAN RAMAKRISHNAN·Filed 2011·Granted Sep 10, 2013·0 cites·13 claims
- 4057US7487421B2Emulation cache access for tag view readsTEXAS INSTRUMENTS INC·Filed 2006·Granted Feb 3, 2009·3 cites·5 claims
- 4157US2012290755A1Lookahead Priority Collection to Support Priority ElevationCHACHAD ABHIJEET ASHOK·Filed 2011·Application pending·0 cites
- 4255US7805644B2Multiple pBIST controllersTEXAS INSTRUMENTS INC·Filed 2007·Granted Sep 28, 2010·2 cites·13 claims
- 4354USRE46193EDistributed power control for controlling power consumption based on detected activity of logic blocksTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 1, 2016·0 cites·14 claims
- 4454US9075744B2Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirtyTRAN JONATHAN SON HUNG·Filed 2011·Granted Jul 7, 2015·0 cites·4 claims
- 4554US8970267B2Asynchronous clock dividers to reduce on-chip variations of clock timingDAMODARAN RAGURAM·Filed 2010·Granted Mar 3, 2015·1 cites·4 claims
- 4651US9582285B2Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Granted Feb 28, 2017·0 cites·20 claims
- 4751US9390011B2Zero cycle clock invalidate operationTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 12, 2016·0 cites·5 claims
- 4846US9965395B2Memory attribute sharing between differing cache levels of multilevel cacheTEXAS INSTRUMENTS INC·Filed 2015·Granted May 8, 2018·0 cites·15 claims
- 4946US8582384B1Process variability tolerant programmable memory controller for a pipelined memory systemTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 12, 2013·0 cites·5 claims
- 5046US2015006820A1Dynamic management of write-miss buffer to reduce write-miss trafficTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →