Memory attribute sharing between differing cache levels of multilevel cache

Abstract

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

What is claimed is: 
     
       1. A data processing system comprising:
 a central processing unit executing program instructions to manipulate data; 
 a first level data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; 
 a first level data cache controller connected to said first level data cache controlling data transfers into and out of said first level data cache; 
 a second level cache connected to said first level cache including second level cache temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; 
 a second level data cache controller connected to said second level data cache controlling data transfers into and out of said second level data cache, said second level cache controller including a plurality of first memory attribute registers each storing a plurality of memory access attributes for a corresponding address range of external memory including cacheability bits; and 
 wherein said first level data cache controller further includes a plurality of second memory attribute registers, each second memory attribute register storing a copy of said cacheability bits of a corresponding one of said plurality of first memory attribute registers for said corresponding address range of external memory. 
 
     
     
       2. The data processing system of  claim 1 , wherein:
 upon a central processing unit write generating a miss in said first level data cache, said first level cache controller operable to
 read cacheability bits from a second memory attribute register having a corresponding address range of external memory including a write address of said central processing unit write, 
 immediately writing to external memory if said cacheability bits indicate non-cacheable, and 
 merging a plurality of such central processing unit writes before writing to external memory if said cacheability bits indicate cacheable. 
 
 
     
     
       3. The data processing system of  claim 1 , wherein:
 upon a central processing unit read generating a miss in said first level data cache, said first level cache controller operable to
 read cacheability bits from a second memory attribute register having a corresponding address range of external memory including a read address of said central processing unit read, 
 identifying a cache line in said first level data cache for replacement and writing said identified cache line to external memory if dirty and if said cacheability bits indicated cacheable, and 
 not identifying a cache line in said first level data cache for replacement if said cacheability bits indicated non-cacheable. 
 
 
     
     
       4. The data processing system of  claim 1 , wherein:
 said memory access attributes stored in said plurality first memory attribute registers include whether write-through is enabled for the corresponding address range of external memory. 
 
     
     
       5. The data processing system of  claim 1 , wherein:
 said memory access attributes stored in said plurality first memory attribute registers include whether external caching is enabled for the corresponding address range of external memory. 
 
     
     
       6. The data processing system of  claim 1 , wherein:
 said memory access attributes stored in said plurality first memory attribute registers include whether cache prefetch is enabled for the corresponding address range of external memory.