Inventor
MACIEJEWSKI EDWARD P
US32 patents
⚠️ This page may combine multiple inventors who share the name “MACIEJEWSKI EDWARD P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS6991979B2Jan 31, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM52 citations96
US6249029B1Jun 19, 2001
Device method for enhanced avalanche SOI CMOS
IBM54 citations96
US5959335ASep 28, 1999
Device design for enhanced avalanche SOI CMOS
IBM67 citations96
US8354309B2Jan 15, 2013
Method of providing threshold voltage adjustment through gate dielectric stack modification
IBM24 citations92
US6972614B2Dec 6, 2005
Circuits associated with fusible elements for establishing and detecting of the states of those elements
IBM35 citations89
US7504875B2Mar 17, 2009
Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit
IBM10 citations84
US7295057B2Nov 13, 2007
Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit
IBM11 citations84
US7242072B2Jul 10, 2007
Electrically programmable fuse for silicon-on-insulator (SOI) technology
IBM15 citations84
US6692998B2Feb 17, 2004
Integrated high quality diode
IBM18 citations84
US9431339B2Aug 30, 2016
Wiring structure for trench fuse component with methods of fabrication
IBM5 citations82
US7091128B2Aug 15, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM6 citations73
US6980009B2Dec 27, 2005
Structure for measurement of capacitance of ultra-thin dielectrics
IBM10 citations73
US7354805B2Apr 8, 2008
Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology
IBM2 citations63
US7408421B2Aug 5, 2008
Determining thermal absorption using ring oscillator
IBM2 citations60
US7227204B2Jun 5, 2007
Structure for improved diode ideality
IBM6 citations58
US9209200B2Dec 8, 2015
Methods for forming a self-aligned maskless junction butting for integrated circuits
IBM0 citations52
US9064972B2Jun 23, 2015
Method of forming a gated diode structure for eliminating RIE damage from cap removal
IBM0 citations52
US8796771B2Aug 5, 2014
Creating anisotropically diffused junctions in field effect transistor devices
IBM0 citations52
US7583125B2Sep 1, 2009
Methods and apparatus for pulse generation used in characterizing electronic fuses
IBM0 citations52
US7396694B2Jul 8, 2008
Structure for monitoring semiconductor polysilicon gate profile
IBM0 citations51
US7135346B2Nov 14, 2006
Structure for monitoring semiconductor polysilicon gate profile
IBM0 citations51
US9431340B2Aug 30, 2016
Wiring structure for trench fuse component with methods of fabrication
IBM1 citations50
US8980720B2Mar 17, 2015
eFUSE and method of fabrication
IBM0 citations46