Inventor

EICKHOFF SUSAN M

US18 patents

⚠️ This page may combine multiple inventors who share the name “EICKHOFF SUSAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EICKHOFF SUSAN M

IBM

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Partial data replay in a distributed memory buffer system

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Interface scheduler for a distributed memory system

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Partial data replay in a distributed memory buffer system

Double data rate (DDR) memory read latency reduction

JTAG support over a broadcast bus in a distributed memory buffer system

Host controlled data chip address sequencing for a distributed memory buffer system

Reducing chip latency at a clock boundary by reference clock phase adjustment

Register access in a distributed memory buffer system

BAUMGARTNER STEVEN J

Parallel data communications mechanism having reduced power continuously calibrated lines