Inventor

PORZIO LUCA

IT87 patents

⚠️ This page may combine multiple inventors who share the name “PORZIO LUCA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PORZIO LUCA

MICRON TECHNOLOGY INC

Apparatuses and methods for memory operations having variable latencies

Apparatuses and methods for memory operations having variable latencies

Apparatuses and methods for variable latency memory operations

Apparatuses and methods for memory operations having variable latencies

Methods and apparatuses for executing a plurality of queued tasks in a memory

Apparatuses and methods for variable latency memory operations

Methods and apparatuses for requesting ready status information from a memory

Apparatuses and methods for variable latency memory operations

Apparatuses and methods for performing write count threshold wear leveling operations

Apparatuses and methods for memory operations having variable latencies

Apparatuses and methods for providing data to a configurable storage area

Apparatuses and methods for providing data to a configurable storage area

Apparatuses and methods for providing data from a buffer

Apparatuses and methods for providing data from a buffer

Optimized command sequences

Detecting page fault traffic

Hybrid memory system interface

Apparatuses and methods for memory operations having variable latencies

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Memory devices for detecting known initial states and related methods and electronic systems

Storage traffic pattern detection in memory devices

Apparatuses and methods for providing data to a configurable storage area

Memory sub-system managing remapping for misaligned memory components

Memory sub-system managing remapping for misaligned memory components

Dynamic parity scheme

Write booster buffer and hibernate

Write booster buffer and hibernate

Hybrid memory system interface

Memory device access techniques

Methods and apparatuses for requesting ready status information from a memory

Storage class memory status

Identification and storage of boot information at a memory system

Techniques for atomic write operations

Reading sequential data using mapping information stored at a host device

Determining available resources for storing data

Detecting page fault traffic

Techniques for atomic write operations

Identification and storage of boot information at a memory system

Determining available resources for storing data

Reading sequential data using mapping information stored at a host device

Memory device performance based on storage traffic pattern detection

Storage traffic pattern detection in memory devices

Detecting page fault traffic

LODESTAR LICENSING GROUP LLC

Storage traffic pattern detection in memory devices

Integrated pivot table in a logical-to-physical mapping

Integrated pivot table in a logical-to-physical mapping

PORZIO LUCA

Concurrent memory operations

FURNO ANTONIO

Selective error control coding in memory devices