Integrated pivot table in a logical-to-physical mapping
Abstract
Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a read command comprising a first address of the memory device;
read, based at least in part on receiving the read command, a first entry of a mapping between the first address and a second address;
read, based at least in part on reading the first entry, a second entry of the mapping, the second entry comprising at least a portion of a pivot table associated with second addresses of the memory device; and
transmit data retrieved from the second address identified in the pivot table based at least in part on identifying the second address.
2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to:
retrieve, from the memory device, the data from the second address identified using the pivot table of the second entry, wherein transmitting the data is based at least in part on retrieving the data.
3. The apparatus of claim 2 , wherein the data is retrieved from the second address without reading a third entry of the mapping.
4. The apparatus of claim 1 , wherein the second entry is associated with a first subset of the mapping and comprises a flag that indicates whether the second entry is associated with a second subset of the mapping or is associated with a starting physical address of a set of physical addresses associated with the read command.
5. The apparatus of claim 4 , wherein the controller is further configured to cause the apparatus to:
determine whether physical addresses of the set of physical addresses are consecutively indexed based at least in part on reading the second entry of the mapping, wherein transmitting the data is based at least in part on determining that the physical addresses are consecutively indexed.
6. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to:
identify a starting physical address of a plurality of physical addresses that are consecutively indexed using the pivot table of the second entry; and
identify a physical address to access based at least in part on a starting logical block address and a difference between the starting logical block address and the first address.
7. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to:
refrain from reading a third entry of the mapping based at least in part on a flag indicating that the second entry of the mapping is associated with the second addresses of the memory device.
8. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to:
refrain from transferring, from the memory device to a second memory device, at least a portion of a subset of the mapping based at least in part on a flag indicating that the second entry of the mapping is associated with the second addresses of the memory device.
9. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a plurality of write commands for a set of first addresses of the memory device;
determine an indexing of the set of first addresses based at least on receiving the plurality of write commands;
set, based at least in part on the indexing, a flag in an entry of a mapping, the entry comprising at least a portion of a pivot table associated with the set of first addresses; and
write data to the set of first addresses based at least in part on setting the flag.
10. The apparatus of claim 9 , wherein the flag that indicates whether the entry is associated with a particular portion of the mapping or is associated with a starting first address of the set of first addresses associated with the plurality of write commands.
11. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
set the entry of the mapping to indicate a starting first address based at least in part on determining that the set of first addresses are consecutively indexed.
12. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
identify that the pivot table is included in a particular portion of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on identifying the pivot table.
13. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
generate the pivot table based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on generating the pivot table.
14. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
replace the entry of the mapping comprising a pointer with at least the portion of the pivot table, wherein setting the flag is based at least in part on replacing the entry.
15. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
store at least the portion of the pivot table in the entry of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on storing at least the portion of the pivot table.
16. The apparatus of claim 9 , wherein the pivot table comprises a plurality of entries, a first entry of the plurality of entries represents a plurality of second addresses that are consecutively indexed and identifies a starting first address of a plurality of first addresses that are consecutively indexed, the plurality of first addresses corresponding to the plurality of second addresses.
17. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a plurality of write commands for a set of physical addresses of a non-volatile memory device;
determine whether the set of physical addresses are consecutively indexed based at least on receiving the plurality of write commands;
generate a pivot table to be included in a first subset of a mapping based at least in part on the set of physical addresses being consecutively indexed, the mapping comprising the first subset, a second subset, and a third subset;
set, based at least in part on generating the pivot table, a flag in an entry of the first subset of the mapping, the entry of the first subset comprising at least a portion of the pivot table associated with the set of physical addresses; and
output data to the set of physical addresses based at least in part on setting the flag.
18. The apparatus of claim 17 , wherein the first subset comprises a global mapping, the second subset comprises a root mapping, and the third subset comprises a physical page table mapping.
19. The apparatus of claim 17 , wherein a size of the second subset of the mapping is increased based at least in part on including the pivot table in the first subset of the mapping.
20. The apparatus of claim 17 , wherein the pivot table comprises a plurality of entries, a first entry of the plurality of entries represents a plurality of logical block addresses that are consecutively indexed and identifies a starting physical address of a plurality of physical addresses that are consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses.Cited by (0)
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