Inventor

D'ELISEO GIUSEPPE

IT36 patents

⚠️ This page may combine multiple inventors who share the name “D'ELISEO GIUSEPPE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

D'ELISEO GIUSEPPE

MICRON TECHNOLOGY INC

Methods and apparatuses for executing a plurality of queued tasks in a memory

NAND data placement schema

Reading sequential data from memory using a pivot table

Clustered parity for NAND data placement schema

Dynamic P2L asynchronous power loss mitigation

NAND data placement schema

Scheme to improve efficiency of device garbage collection in memory devices

Scheme to improve efficiency of garbage collection in cached flash translation layer

NAND logical-to-physical table region tracking

Hybrid logical to physical caching scheme

Controlling NAND operation latency

Controlling NAND operation latency

Controlling NAND operation latency

Reading sequential data from memory using a pivot table

Clustered parity for NAND data placement schema

NAND data placement schema

Partial superblock memory management

Dynamic P2L asynchronous power loss mitigation

Integrated pivot table in a logical-to-physical mapping having entries and subsets associated via a flag

Methods and apparatuses for executing a plurality of queued tasks in a memory

Hybrid logical to physical caching scheme of L2P cache and L2P changelog

Synchronizing NAND logical-to-physical table region tracking

Synchronizing NAND logical-to-physical table region tracking

Adaptive block mapping

Data relocation operation techniques

Adaptive block mapping

Data relocation operation techniques

Data block refresh during read access

Setting switching for single-level cells

Corrupted storage portion recovery in a memory device

Cache read context switching in a memory sub-system

Direct logical-to-physical address mapping for sequential physical addresses

LODESTAR LICENSING GROUP LLC

Integrated pivot table in a logical-to-physical mapping

Integrated pivot table in a logical-to-physical mapping

NAND logical-to-physical table region tracking

IACULO MASSIMO

Preparation of memory device for access using memory access type indicator signal