Inventor

HUNG JUI-PIN

TW137 patents

⚠️ This page may combine multiple inventors who share the name “HUNG JUI-PIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUNG JUI-PIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Package on package (PoP) bonding structures

Integrated fan-out structure with guiding trenches in buffer layer

Semiconductor structure and manufacturing method thereof

Three-layer Package-on-Package structure and method forming same

Interconnect structure for package-on-package devices and a method of fabricating

Interconnect structure for wafer level package

Interconnect structure for package-on-package devices and a method of fabricating

Method of forming a semiconductor package

Interconnect structure for package-on-package devices

Interconnect structure for package-on-package devices

Semiconductor package

Interconnect structure for package-on-package devices

Semiconductor package structure

Semiconductor structure and manufacturing method thereof

Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

Semiconductor package and manufacturing method of the same

Semiconductor package device and manufacturing method thereof

Integrated fan-out structure with guiding trenches in buffer layer

Structure and formation method for chip package

Semiconductor package structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG

Package with metal-insulator-metal capacitor and method of manufacturing the same

Method of fabricating interconnect structure for package-on-package devices

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

Package with a fan-out structure and method of forming the same

Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

Chip on package structure and method

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Fan out package, semiconductor device and manufacturing method thereof

Package on package (PoP) bonding structures

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

Interconnect structure for wafer level package

Integrated fan-out package structures with recesses in molding compound

Semiconductor device and manufacturing method thereof

Multi-chip package and method of formation

Package for three dimensional integrated circuit

Adhesion between post-passivation interconnect structure and polymer

YU CHEN-HUA

Interconnect structure for wafer level package

Multi-chip fan out package and methods of forming the same

Semiconductor package with through silicon vias

Multiple die packaging interposer structure and method

LIN JING-CHENG

Wafer-level packaging mechanisms

Packaged semiconductor device with a molding compound and a method of forming the same

Packages including active dies and dummy dies and methods for forming the same

Three dimensional (3D) fan-out packaging mechanisms

HUNG JUI-PIN

Packaging methods and structures using a die attach film

Packaging methods for semiconductor devices

HSIAO YI-LI

Wafer&#39;s ambiance control

Apparatus for storing substrates

Wafer's ambiance control