Inventor

YU KAI HUNG

US36 patents

⚠️ This page may combine multiple inventors who share the name “YU KAI HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU KAI HUNG

TOKYO ELECTRON LTD

Three-dimensional device and method of forming the same

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Selective deposition with surface treatment

Platform and method of operating for integrated end-to-end CMP-less interconnect process

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Selective bottom-up metal feature filling for interconnects

Selective deposition of conductive cap for fully-aligned-via (FAV)

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization

Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling

Copper wiring forming method, film forming system, and storage medium

Method of conductive material deposition

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Method of bottom-up metallization in a recessed feature

Interconnect structure and method of forming the same

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Method of integrated circuit fabrication with dual metal power rail

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Metal hard mask layers for processing of microelectronic workpieces

Variable hardness amorphous carbon mask

Interconnect structure and method of forming the same

Sacrificial gate capping layer for gate protection during source/drain contact opening

Method of self-aligned dielectric wall formation for forksheet application

Method for using ultra thin ruthenium metal hard mask for etching profile control

Ruthenium metal feature fill for interconnects

Ruthenium metal feature fill for interconnects

Ruthenium metal feature fill for interconnects

Methods and structures for improving etch profile of underlying layers

Selective inhibition for selective metal deposition

Thermal etching of ruthenium

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Removal method and processing method

PERICOM SEMICONDUCTOR CORP

Referenceless clock and data recovery circuits

Repeaters with fast transitions from low-power standby to low-frequency signal transmission

Referenceless clock and data recovery circuits

DIODES INC

Multipath clock and data recovery