Inventor

GROSZ NADAV

US54 patents

⚠️ This page may combine multiple inventors who share the name “GROSZ NADAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GROSZ NADAV

MICRON TECHNOLOGY INC

Methods and system with dynamic ECC voltage and frequency

Large data read techniques

Large data read techniques

Host-resident translation layer validity check techniques

Sequential data optimized sub-regions in storage devices

Methods and system with dynamic ECC voltage and frequency

Read prediction during a system boot procedure

Transferring memory system data to a host system

Host timeout avoidance in a memory device

Host assisted operations in managed memory devices

Automated power down based on state of firmware

Logical-to-physical map synchronization in a memory device

Mapping table compression using a run length encoding algorithm

Host adaptive memory device optimization

Host timeout avoidance in a memory device

Sequential data optimized sub-regions in storage devices

Automated power down based on state of firmware

Host inquiry response generation in a memory device

Adaptive watchdog in a memory device

Host adaptive memory device optimization

Host inquiry response generation in a memory device

Remapping techniques for a range of logical block addresses in a logical to physical table of NAND storage

Adaptive watchdog in a memory device

Cryptographic data integrity protection

Shallow hibernate power state

Flash memory persistent cache techniques

Fast purge on storage devices

Shallow hibernate power state

Automated power down based on state of firmware

Sequential data optimized sub-regions in storage devices

Methods and system with dynamic ECC voltage and frequency

Large data read techniques

Facilitating sequential reads in memory sub-systems

Cryptographic data integrity protection

Increased efficiency obfuscated logical-to-physical map management

Fast purge on storage devices

Facilitating sequential reads in memory sub-systems

Flash memory persistent cache techniques

Debugging a semiconductor device

Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses

Multi-tier cache for a memory system

LODESTAR LICENSING GROUP LLC

Host assisted operations in managed memory devices

Large data read techniques

Sequential data optimized sub-regions in storage devices

Methods and system with dynamic ECC voltage and frequency

Increased efficiency obfuscated logical-to-physical map management

Host assisted operations in managed memory devices

Large data read techniques

Logical-to-physical map synchronization in a memory device

Increased efficiency obfuscated logical-to-physical map management