Host timeout avoidance in a memory device

Abstract

Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

The invention claimed is: 
     
       1. A method for preventing host resets at a memory device, the method comprising:
 using one or more processors of the memory device to perform operations comprising: 
 receiving, a memory device command from a host device, the memory device command comprising a multi-block read or write command; 
 determining a host timeout value associated with the memory device command, the host timeout value being a previously observed amount of time between issuance of the memory device command and issuance of a subsequent host reset command to the memory device; 
 initializing a timer of the memory device to a value based upon the host timeout value to monitor a time interval from receipt of the memory device command; 
 causing the memory device command to be executed; 
 determining that the timer either has expired or is within a predetermined time before expiry and the memory device command has not finished executing; and 
 responsive to determining that the timer either has expired or is within a predetermined time before expiry, and that the memory device command has not finished executing: 
 obtaining a partial result of the memory device command, the partial result less than a complete result of the memory device command, the partial result comprising results from a plurality of blocks read from or written to; 
 transmitting a response to the memory device command to the host device, wherein the response includes the partial result; 
 finishing executing the memory device command; and 
 transmitting a second response to the memory device command to the host device, wherein the response includes the remaining results. 
 
     
     
       2. The method of  claim 1 , wherein determining the host timeout value comprises:
 determining a class of the memory device command; and 
 accessing a list of stored host timeout values, each stored host timeout value in the list associated with a different class of memory device commands, by using the class of the memory device command as an index into the list to determine the host timeout value. 
 
     
     
       3. The method of  claim 2 , wherein a stored host timeout value for a multiple block read or write command is greater than a stored host timeout value for a single block read or write command. 
     
     
       4. The method of  claim 2  further comprising:
 receiving a second memory device command at the memory device; 
 measuring a second host timeout value between receipt of the second memory device command at the memory device and when a host reset signal associated with the second memory device command was received at the memory device; and 
 populating to the list of stored host timeout values, the measured second host timeout value for the second memory device command. 
 
     
     
       5. The method of  claim 1 , wherein the response is transmitted to the host device to cause the host device to reset a timer of the host device. 
     
     
       6. The method of  claim 1 , wherein the memory device comprises a NAND storage device. 
     
     
       7. The method of  claim 1 , wherein determining that the timer either has expired or is within a predetermined time before expiry comprises receiving an interrupt. 
     
     
       8. A memory system, comprising:
 control circuitry configured to perform operations comprising: 
 receiving, a memory device command from a host device, the memory device command comprising a multi-block read or write command; 
 determining a host timeout value associated with the memory device command, the host timeout value being a previously observed amount of time between issuance of the memory device command and issuance of a subsequent host reset command to the memory system; 
 initializing a timer of the memory system to a value based upon the host timeout value to monitor a time interval from receipt of the memory device command; 
 causing the memory device command to be executed; 
 determining that the timer either has expired or is within a predetermined time before expiry and the memory device command has not finished executing; and 
 responsive to determining that the timer either has expired or is within a predetermined time before expiry, and that the memory device command has not finished executing: 
 obtaining a partial result of the command, the partial result less than a complete result of the memory device command, the partial result comprising results from a plurality of blocks read from or written to; 
 transmitting a response to the memory device command to the host device, wherein the response includes the partial result; 
 finishing executing the memory device command; and 
 transmitting a second response to the memory device command to the host device, wherein the response includes the remaining results. 
 
     
     
       9. The memory system of  claim 8 , wherein the operations of determining the host timeout value comprises:
 determining a class of the memory device command; and 
 accessing a list of stored host timeout values, each stored host timeout value in the list associated with a different class of memory device commands, by using the class of the memory device command as an index into the list to determine the host timeout value. 
 
     
     
       10. The memory system of  claim 9 , wherein a stored host timeout value for a multiple block read or write command is greater than a stored host timeout value for a single block read or write command. 
     
     
       11. The memory system of  claim 9 , wherein the operations further comprise:
 receiving a second memory device command at the memory system; 
 measuring a second host timeout value between receipt of the second memory device command at the memory system and when a host reset signal associated with the second memory device command was received at the memory system; and 
 populating to the list of stored host timeout values, the measured second host timeout value for the second memory device command. 
 
     
     
       12. The memory system of  claim 8 , wherein the response is transmitted to the host device to cause the host device to reset a timer of the host device. 
     
     
       13. The memory system of  claim 8 , wherein the memory system comprises a NAND storage device. 
     
     
       14. The memory system of  claim 8 , wherein the operations of determining that the timer either has expired or is within a predetermined time before expiry comprises receiving an interrupt. 
     
     
       15. A non-transitory machine-readable medium, comprising instructions for preventing host resets, the instructions, when executed by a processor of a memory device, cause the process to perform operations comprising:
 receiving, a memory device command from a host device, the memory device command comprising a multi-block read or write command; 
 determining a host timeout value associated with the memory device command, the host timeout value being a previously observed amount of time between issuance of the memory device command and issuance of a subsequent host reset command to the memory device; 
 initializing a timer of the memory device to a value based upon the host timeout value to monitor a time interval from receipt of the memory device command; 
 causing the memory device command to be executed; 
 determining that the timer either has expired or is within a predetermined time before expiry and the memory device command has not finished executing; and 
 responsive to determining that the timer either has expired or is within a predetermined time before expiry, and that the memory device command has not finished executing: 
 obtaining a partial result of the memory device command, the partial result less than a complete result of the command, the partial result comprising results from a plurality of blocks read from or written to; 
 transmitting a response to the memory device command to the host device, wherein the response includes the partial result; 
 finishing executing the memory device command; and 
 transmitting a second response to the command to the host device, wherein the response includes the remaining results. 
 
     
     
       16. The non-transitory machine-readable medium of  claim 15 , wherein the operations of determining the host timeout value comprises:
 determining a class of the memory device command; and 
 accessing a list of stored host timeout values, each stored host timeout value in the list associated with a different class of memory device commands, by using the class of the memory device command as an index into the list to determine the host timeout value. 
 
     
     
       17. The non-transitory machine-readable medium of  claim 16 , wherein a stored host timeout value for a multiple block read or write command is greater than a stored host timeout value for a single block read or write command. 
     
     
       18. The non-transitory machine-readable medium of  claim 16 , further comprising:
 receiving a second memory device command at the memory device; 
 measuring a second host timeout value between receipt of the second memory device command at the memory device and when a host reset signal associated with the second memory device command was received at the memory device; and 
 populating to the list of stored host timeout values, the measured second host timeout value for the second memory device command.