Inventor

GULER LEONARD P

US72 patents

Patents

50 patents

US11855223B2Dec 26, 2023

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

INTEL CORP6 citations86

US11233152B2Jan 25, 2022

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

INTEL CORP6 citations86

US12342612B2Jun 24, 2025

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

INTEL CORP2 citations75

US12266708B2Apr 1, 2025

Integrated circuit structures having dielectric anchor void

INTEL CORP2 citations75

US11862635B2Jan 2, 2024

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

INTEL CORP2 citations73

US11398474B2Jul 26, 2022

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

INTEL CORP4 citations73

US11302790B2Apr 12, 2022

Fin shaping using templates and integrated circuit structures resulting therefrom

INTEL CORP3 citations73

US10559529B2Feb 11, 2020

Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

INTEL CORP6 citations73

US10541143B2Jan 21, 2020

Self-aligned build-up of topographic features

INTEL CORP4 citations73

US10522402B2Dec 31, 2019

Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom

INTEL CORP3 citations73

US11043492B2Jun 22, 2021

Self-aligned gate edge trigate and finFET devices

INTEL CORP4 citations71

US12364002B2Jul 15, 2025

Integrated circuit structures having metal gates with tapered plugs

INTEL CORP2 citations69

US12557625B2Feb 17, 2026

Spacer self-aligned via structures using directed self assembly for gate contact or trench contact

INTEL CORP1 citations64

US12563774B2Feb 24, 2026

FIN shaping using templates and integrated circuit structures resulting therefrom

INTEL CORP0 citations63

US11742410B2Aug 29, 2023

Gate-all-around integrated circuit structures having oxide sub-fins

INTEL CORP0 citations63

US11715775B2Aug 1, 2023

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

INTEL CORP0 citations63

US11355608B2Jun 7, 2022

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

INTEL CORP0 citations63

US11164790B2Nov 2, 2021

Integrated nanowire and nanoribbon patterning in transistor manufacture

INTEL CORP0 citations63

US12581927B2Mar 17, 2026

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

INTEL CORP0 citations62

US12532538B2Jan 20, 2026

Integrated circuit structures having conductive structures in fin isolation regions

INTEL CORP0 citations62

US12453160B2Oct 21, 2025

Deep etch processing for transistors having varying pitch

INTEL CORP0 citations62

US12419085B2Sep 16, 2025

Integrated circuit structures having backside gate tie-down

INTEL CORP0 citations62

US12400913B2Aug 26, 2025

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

INTEL CORP0 citations62

US12382706B2Aug 5, 2025

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

INTEL CORP0 citations62

US12364001B2Jul 15, 2025

Integrated circuit structures with backside gate partial cut or trench contact partial cut

INTEL CORP0 citations62

US12224350B2Feb 11, 2025

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

INTEL CORP0 citations62

US12080639B2Sep 3, 2024

Contact over active gate structures with metal oxide layers to inhibit shorting

INTEL CORP1 citations62

US11527433B2Dec 13, 2022

Via and plug architectures for integrated circuit interconnects and methods of manufacture

INTEL CORP1 citations62

US12598803B2Apr 7, 2026

Integrated circuit structures having gate cut offset

INTEL CORP0 citations61

US12527078B2Jan 13, 2026

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation

INTEL CORP0 citations61

US12501684B2Dec 16, 2025

Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact

INTEL CORP0 citations61

US12249541B2Mar 11, 2025

Vertical edge blocking (VEB) technique for increasing patterning process margin

INTEL CORP0 citations61

US11594448B2Feb 28, 2023

Vertical edge blocking (VEB) technique for increasing patterning process margin

INTEL CORP0 citations61

US11581315B2Feb 14, 2023

Self-aligned gate edge trigate and finFET devices

INTEL CORP0 citations61

US11227863B2Jan 18, 2022

Gate isolation in non-planar transistors

INTEL CORP0 citations61

US11056397B2Jul 6, 2021

Directional spacer removal for integrated circuit structures

INTEL CORP0 citations61

US12563779B2Feb 24, 2026

Gate-all-around integrated structures having gate height reduction and dielectric capping material with shoulder portions inside gate stack

INTEL CORP0 citations60

US12507464B2Dec 23, 2025

Gate aligned fin cut for advanced integrated circuit structure fabrication

INTEL CORP0 citations60

US12457771B2Oct 28, 2025

Plug and recess process for dual metal gate on stacked nanoribbon devices

INTEL CORP0 citations60

US12046652B2Jul 23, 2024

Plug and recess process for dual metal gate on stacked nanoribbon devices

INTEL CORP0 citations60

US11972979B2Apr 30, 2024

1D vertical edge blocking (VEB) via and plug

INTEL CORP0 citations60

US11721580B2Aug 8, 2023

1D vertical edge blocking (VEB) via and plug

INTEL CORP0 citations60

US11594637B2Feb 28, 2023

Gate-all-around integrated circuit structures having fin stack isolation

INTEL CORP0 citations60

US11569370B2Jan 31, 2023

DEPOP using cyclic selective spacer etch

INTEL CORP0 citations60

US12471349B2Nov 11, 2025

Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication

INTEL CORP0 citations59

Showing the top 50 of 72 patents by PatentIndex Score.

GULER LEONARD P

Patents

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Integrated circuit structures having dielectric anchor void

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Fin shaping using templates and integrated circuit structures resulting therefrom

Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

Self-aligned build-up of topographic features

Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects and structures resulting therefrom

Self-aligned gate edge trigate and finFET devices

Integrated circuit structures having metal gates with tapered plugs

Spacer self-aligned via structures using directed self assembly for gate contact or trench contact

Integrated circuit structures with deep via structure

Integrated circuit structures having dielectric anchor void

Integrated circuit structures with backside gate cut or trench contact cut

Gate-all-around integrated circuit structures having oxide sub-fins

Integrated nanowire and nanoribbon patterning in transistor manufacture

FIN shaping using templates and integrated circuit structures resulting therefrom

Gate-all-around integrated circuit structures having oxide sub-fins

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Integrated nanowire and nanoribbon patterning in transistor manufacture

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

Integrated circuit structures having conductive structures in fin isolation regions

Deep etch processing for transistors having varying pitch

Integrated circuit structures having backside gate tie-down

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Integrated circuit structures with backside gate partial cut or trench contact partial cut

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Contact over active gate structures with metal oxide layers to inhibit shorting

Via and plug architectures for integrated circuit interconnects and methods of manufacture

Integrated circuit structures having gate cut offset

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation

Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact

Vertical edge blocking (VEB) technique for increasing patterning process margin

Vertical edge blocking (VEB) technique for increasing patterning process margin

Self-aligned gate edge trigate and finFET devices

Gate isolation in non-planar transistors

Directional spacer removal for integrated circuit structures

Gate-all-around integrated structures having gate height reduction and dielectric capping material with shoulder portions inside gate stack

Gate aligned fin cut for advanced integrated circuit structure fabrication

Plug and recess process for dual metal gate on stacked nanoribbon devices

Plug and recess process for dual metal gate on stacked nanoribbon devices

1D vertical edge blocking (VEB) via and plug

1D vertical edge blocking (VEB) via and plug

Gate-all-around integrated circuit structures having fin stack isolation

DEPOP using cyclic selective spacer etch

Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication