Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Abstract

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

What is claimed is: 
     
       1. An integrated circuit structure, comprising:
 a semiconductor fin above a substrate and having a length in a first direction; 
 a nanowire over the semiconductor fin; 
 a gate structure over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction; and 
 a pair of gate endcap isolation structures, wherein a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin, wherein the first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure. 
 
     
     
       2. The integrated circuit structure of  claim 1 , further comprising:
 source and drain regions adjacent the nanowire and the semiconductor fin, on either side of the gate structure; and 
 a first trench contact over the source region and a second trench contact over the drain region. 
 
     
     
       3. The integrated circuit structure of  claim 1 , further comprising:
 a second semiconductor fin above the substrate and having a length in the first direction, the second semiconductor fin spaced apart from the first semiconductor fin; 
 a second nanowire over the second semiconductor fin; 
 a second gate structure over the second nanowire and the second semiconductor fin, the second gate structure having a first end opposite a second end in the second direction, wherein the second of the pair of gate endcap isolation structures is directly adjacent to the first end of the second gate structure; and 
 a third gate endcap isolation structure directly adjacent to the second end of the second gate structure, wherein the third gate endcap isolation structure and the second of the pair of gate endcap isolation structures are centered with the second semiconductor fin. 
 
     
     
       4. The integrated circuit structure of  claim 3 , further comprising:
 a local interconnect above and electrically coupling the gate structure and second gate structure. 
 
     
     
       5. The integrated circuit structure of  claim 3 , wherein the second nanowire is wider than the nanowire. 
     
     
       6. The integrated circuit structure of  claim 1 , wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode. 
     
     
       7. The integrated circuit structure of  claim 1 , wherein the pair of gate endcap isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and a combination thereof. 
     
     
       8. The integrated circuit structure of  claim 1 , wherein the pair of gate endcap isolation structure comprise a lower dielectric portion and a dielectric cap on the lower dielectric portion. 
     
     
       9. The integrated circuit structure of  claim 1 , wherein at least one of the pair of gate endcap isolation structures comprises a vertical seam centered therein. 
     
     
       10. An integrated circuit structure, comprising:
 a first fin having a longest dimension along a first direction; 
 a first nanowire over the first fin; 
 a second fin having a longest dimension along the first direction; 
 a second nanowire over the second fin; 
 a first gate structure over the first nanowire and the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction; 
 a second gate structure over the second nanowire and over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure discontinuous with the first gate structure along the second direction, and the second gate structure having an edge facing an edge of the first gate structure along the second direction; and 
 a gate endcap isolation structure between and in contact with the edge of the first gate structure and the edge of the second gate structure along the second direction, the gate endcap isolation structure having a length along the first direction greater than a length of the first gate structure and the second gate structure along the first direction. 
 
     
     
       11. The integrated circuit structure of  claim 10 , wherein the second nanowire is wider than the nanowire. 
     
     
       12. The integrated circuit structure of  claim 10 , wherein the gate endcap isolation structure comprise a lower dielectric portion and a dielectric cap on the lower dielectric portion. 
     
     
       13. The integrated circuit structure of  claim 10 , wherein the gate endcap isolation structure comprises a vertical seam centered therein. 
     
     
       14. The integrated circuit structure of  claim 10 , further comprising:
 a dielectric material laterally adjacent to and in contact with the gate endcap isolation structure, and the dielectric material having a composition different than a composition of the gate endcap isolation structure. 
 
     
     
       15. The integrated circuit structure of  claim 10 , wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode, and wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode. 
     
     
       16. The integrated circuit structure of  claim 15 , wherein the gate endcap isolation structure is in contact with the gate dielectric layer of the first gate structure and with the gate dielectric layer of the second gate structure. 
     
     
       17. The integrated circuit structure of  claim 10 , wherein the gate endcap isolation structure has a height greater than a height of the first gate structure and greater than a height of the second gate structure. 
     
     
       18. The integrated circuit structure of  claim 17 , further comprising:
 a local interconnect over a portion of the first gate structure, over a portion of the gate endcap isolation structure, and over a portion of the second gate structure. 
 
     
     
       19. The integrated circuit structure of  claim 18 , wherein the local interconnect electrically couples the first gate structure to the second gate structure. 
     
     
       20. The integrated circuit structure of  claim 19 , further comprising:
 a gate contact on a portion of the local interconnect over the first gate structure, but not on a portion of the local interconnect over the second gate structure. 
 
     
     
       21. An integrated circuit structure, comprising:
 a first semiconductor fin and nanowire pair having a cut along a length of the first semiconductor fin and nanowire pair; 
 a second semiconductor fin and nanowire pair having a cut along a length of the second semiconductor fin and nanowire pair; and 
 a gate endcap isolation structure between the first semiconductor fin and nanowire pair and the second semiconductor fin and nanowire pair, the gate endcap isolation structure having a substantially uniform width along the lengths of the first and second semiconductor fin and nanowire pairs. 
 
     
     
       22. The integrated circuit structure of  claim 21 , wherein the gate endcap isolation structure comprises a lower dielectric portion and a dielectric cap on the lower dielectric portion. 
     
     
       23. The integrated circuit structure of  claim 21 , wherein the gate endcap isolation structure comprises a vertical seam centered within the gate endcap isolation structure.