Inventor

GUHA BISWAJEET

US108 patents

⚠️ This page may combine multiple inventors who share the name “GUHA BISWAJEET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUHA BISWAJEET

INTEL CORP

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

Cavity spacer for nanowire transistors

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact

Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact

Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact

Wrap-around contact structures for semiconductor nanowires and nanoribbons

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Wrap-around contact structures for semiconductor nanowires and nanoribbons

Source/drain regions in integrated circuit structures

Buried etch-stop layer to help control transistor source/drain depth

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

Fin shaping using templates and integrated circuit structures resulting therefrom

Epitaxial oxide plug for strained transistors

Self-aligned nanowire

Cavity spacer for nanowire transistors

Dielectric isolation layer between a nanowire transistor and a substrate

Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process

High aspect ratio source or drain structures with abrupt dopant profile

Self-aligned gate edge trigate and finFET devices

Integrated circuit structures having partitioned source or drain contact structures

Integrated circuit structures having metal gates with tapered plugs

Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Gate-all-around integrated circuit structures having oxide sub-fins

Integrated nanowire and nanoribbon patterning in transistor manufacture

FIN shaping using templates and integrated circuit structures resulting therefrom

Gate-all-around integrated circuit structures having oxide sub-fins

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Isolation schemes for gate-all-around transistor devices

Sub-Fin isolation schemes for gate-all-around transistor devices

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures

Isolation schemes for gate-all-around transistor devices

Integrated nanowire and nanoribbon patterning in transistor manufacture

Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Source electrode and drain electrode protection for nanowire transistors

KEPLER COMPUTING INC

Diode connected non-linear input capacitors based majority gate

Memory device fabrication through wafer bonding

Method of forming capacitors through wafer bonding

Time decoupled write operations for non-linear polar material based memory

UNIV CORNELL

Fiber-waveguide evanescent coupler

Athermal optical devices based on composite structures

LIPSON MICHAL

Passively-thermally-stabilized photonic apparatus, method, and applications