Inventor
CRUM DAX M
US19 patents
Patents
19 patentsUS11855223B2Dec 26, 2023
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
INTEL CORP6 citations86
US11233152B2Jan 25, 2022
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
INTEL CORP6 citations86
US11018222B1May 25, 2021
Metallization in integrated circuit structures
INTEL CORP16 citations82
US12002810B2Jun 4, 2024
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
INTEL CORP5 citations74
US11527612B2Dec 13, 2022
Gate-all-around integrated circuit structures having vertically discrete source or drain structures
INTEL CORP6 citations74
US11869891B2Jan 9, 2024
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process
INTEL CORP2 citations71
US12382706B2Aug 5, 2025
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
INTEL CORP0 citations62
US12369393B2Jul 22, 2025
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
INTEL CORP0 citations62
US12295170B2May 6, 2025
Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer
INTEL CORP1 citations62
US12224350B2Feb 11, 2025
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
INTEL CORP0 citations62
US11515420B2Nov 29, 2022
Contacts to n-type transistors with X-valley layer over L-valley channels
INTEL CORP0 citations62
US12302632B2May 13, 2025
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process
INTEL CORP0 citations61
US12051698B2Jul 30, 2024
Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer
INTEL CORP0 citations59
US12057491B2Aug 6, 2024
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates
INTEL CORP0 citations52
US11495672B2Nov 8, 2022
Increased transistor source/drain contact area using sacrificial source/drain layer
INTEL CORP0 citations52
US12426307B2Sep 23, 2025
Dual metal gate structures on nanoribbon semiconductor devices
INTEL CORP0 citations50
US12113068B2Oct 8, 2024
Fabrication of gate-all-around integrated circuit structures having additive metal gates
INTEL CORP0 citations50
US12310060B2May 20, 2025
Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances
INTEL CORP0 citations48
US12563782B2Feb 24, 2026
Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers
INTEL CORP0 citations45