Inventor

GHANI TAHIR

US533 patents

⚠️ This page may combine multiple inventors who share the name “GHANI TAHIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GHANI TAHIR

INTEL CORP

Semiconductor transistor having a stressed channel

Semiconductor transistor having a stressed channel

Semiconductor transistor having a stressed channel

Device having spacers for improved salicide resistance on polysilicon gates

Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates

Method of recessing spacers to improved salicide resistance on polysilicon gates

Method for forming an integrated circuit

Self-aligned contacts

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

Method of fabricating a MOS transistor with a raised source/drain extension

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Channel dopant implantation with automatic compensation for variations in critical dimension

Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Integration methods to fabricate internal spacers for nanowire devices

Self-aligned gate edge and local interconnect and method to fabricate same

Selective germanium P-contact metalization through trench

Transistors with high concentration of boron doped germanium

Contact resistance reduction employing germanium overlayer pre-contact metalization

Selective germanium P-contact metalization through trench

Logic chip including embedded magnetic tunnel junctions

Semiconductor transistor having a stressed channel

Contact over active gate structures for advanced integrated circuit structure fabrication

Contact over active gate structures for advanced integrated circuit structure fabrication

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Self-aligned contacts

Semiconductor device having self-aligned epitaxial source and drain extensions

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates

GLASS GLENN A

Selective germanium P-contact metalization through trench

Self-aligned 3-D epitaxial structures for MOS device fabrication

III-V layers for N-type and P-type MOS source-drain contacts

Contact resistance reduction employing germanium overlayer pre-contact metalization

Self-aligned contact metallization for reduced contact resistance

BOHR MARK T

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

KIM SEIYON

Integration methods to fabricate internal spacers for nanowire devices

CMOS nanowire structure

CMOS nanowire structure

CAPPELLANI ANNALISA

Multi-gate semiconductor device with self-aligned epitaxial source and drain

Semiconductor device with isolated body portion

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates

MURTHY ANAND S

Transistors with high concentration of boron doped germanium

Semiconductor device having doped epitaxial region and its methods of fabrication

CEA STEPHEN M

High mobility strained channels for fin-based transistors

Non-planar device having uniaxially strained semiconductor body and method of making same

GOLONZKA OLEG

Gate aligned contact and method to fabricate same

PETHE ABHIJIT JAYANT

Gate contact structure over active gate and method to fabricate same

NIKONOV DMITRI E

Spin torque magnetic integrated circuits and devices therefor