US6777760B1ExpiredUtility

Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates

78
Assignee: INTEL CORPPriority: Nov 13, 1998Filed: Jan 5, 2000Granted: Aug 17, 2004
Est. expiryNov 13, 2018(expired)· nominal 20-yr term from priority
H10D 64/0131Y10S257/90H10P 10/00H10D 84/038H10D 84/014H10D 64/663H10D 30/0223H10D 30/0212
78
PatentIndex Score
13
Cited by
20
References
12
Claims

Abstract

A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A gate electrode comprising: 
       an insulative layer disposed on a substrate;  
       a gate layer disposed on said insulative layer, the gate layer being of uniform width along a height thereof;  
       thin first spacers disposed adjacent to opposite sides of said gate layer;  
       thin second spacers disposed adjacent to opposite sides of said thin first spacers;  
       thin third spacers disposed adjacent to opposite sides of said thin second spacers;  
       thick fourth spacers disposed adjacent to opposite sides of said thin third spacers; and  
       a conductive layer disposed on said gate layer, wherein at least part of the conductive layer is wider than said gate layer.  
     
     
       2. The gate electrode of  claim 1 , wherein the conductive layer has a non-uniform cross-section defined by a narrower base section which is in contact with the gate layer, and a wider top section. 
     
     
       3. The gate electrode of  claim 2 , wherein the thin first spacers and the thin second spacers are deformed to accommodate the wider top section of the conductive layer. 
     
     
       4. The gate electrode of  claim 2 , wherein the part of the conductive layer that is wider than the gate layer rests on at least the first thin spacer. 
     
     
       5. The gate electrode of  claim 1  wherein said insulative layer comprises an oxide. 
     
     
       6. The gate electrode of  claim 5  wherein said gate layer comprises a polysilicon. 
     
     
       7. The gate electrode of  claim 6  wherein said conductive layer comprises a polycide. 
     
     
       8. The gate electrode of  claim 7  wherein said thin first spacers comprise an oxide. 
     
     
       9. The gate electrode of  claim 8  wherein said thin second spacers comprise a nitride. 
     
     
       10. The gate electrode of  claim 9  wherein said thin third spacers comprise an oxide. 
     
     
       11. The gate electrode of  claim 10  wherein said thick fourth spacers comprise a nitride. 
     
     
       12. The gate electrode of  claim 11  wherein said polycide comprises titanium salicide (TiSi 2 ).

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