Inventor · disambiguated record
Steven J. Keating
Also filed as: KEATING STEVEN · KEATING STEVEN J
26 granted patents·2 pending applications·1,379 citations·filing 1998–2013
97Inventor score
Top patents by PatentIndex Score
28 records- 0198US6521964B1Device having spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Feb 18, 2003·241 cites·6 claims
- 0298US6509618B2Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Jan 21, 2003·239 cites·8 claims
- 0398US6506652B2Method of recessing spacers to improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jan 14, 2003·239 cites·9 claims
- 0497US7494858B2Transistor with improved tip profile and method of manufacture thereofINTEL CORP·Filed 2005·Granted Feb 24, 2009·104 cites·15 claims
- 0597US7316949B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2005·Granted Jan 8, 2008·50 cites·13 claims
- 0696US6858483B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2002·Granted Feb 22, 2005·81 cites·8 claims
- 0795US7821044B2Transistor with improved tip profile and method of manufacture thereofINTEL CORP·Filed 2008·Granted Oct 26, 2010·32 cites·34 claims
- 0895US7045407B2Amorphous etch stop for the anisotropic etching of substratesINTEL CORP·Filed 2003·Granted May 16, 2006·159 cites·7 claims
- 0994US6972225B2integrating n-type and P-type metal gate transistorsINTEL CORP·Filed 2004·Granted Dec 6, 2005·54 cites·19 claims
- 1094US6953719B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2004·Granted Oct 11, 2005·62 cites·9 claims
- 1181US6703291B1Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensionsINTEL CORP·Filed 2002·Granted Mar 9, 2004·25 cites·23 claims
- 1281US6593633B2Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Jul 15, 2003·16 cites·4 claims
- 1378US6777760B1Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted Aug 17, 2004·13 cites·12 claims
- 1472US8441097B2Methods to form memory devices having a capacitor with a recessed electrodeSTEIGERWALD JOSEPH M·Filed 2009·Granted May 14, 2013·5 cites·12 claims
- 1571US6188117B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Feb 13, 2001·16 cites·28 claims
- 1670US9224794B2Embedded memory device having MIM capacitor formed in excavated structureINTEL CORP·Filed 2013·Granted Dec 29, 2015·1 cites·6 claims
- 1769US6797622B2Selective etching of polysiliconINTEL CORP·Filed 2002·Granted Sep 28, 2004·14 cites·21 claims
- 1866US7927959B2Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced therebyINTEL CORP·Filed 2008·Granted Apr 19, 2011·3 cites·15 claims
- 1963US8441057B2Embedded memory device having MIM capacitor formed in excavated structureKEATING STEVEN J·Filed 2011·Granted May 14, 2013·1 cites·7 claims
- 2061US7799139B2Chemistry for removal of photo resist, organic sacrificial fill material and etch polymerINTEL CORP·Filed 2007·Granted Sep 21, 2010·1 cites·6 claims
- 2155US6235598B1Method of using thick first spacers to improve salicide resistance on polysilicon gatesINTEL CORP·Filed 1998·Granted May 22, 2001·8 cites·10 claims
- 2247US7211872B2Device having recessed spacers for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 2000·Granted May 1, 2007·1 cites·11 claims
- 2345US2009035911A1Method for forming a semiconductor device having abrupt ultra shallow epi-tip regionsRACHMADY WILLY·Filed 2007·Application pending·0 cites
- 2442US2004036123A1Thin dielectric layers and non-thermal formation thereofFiled 2003·Application pending·0 cites
- 2540US6667232B2Thin dielectric layers and non-thermal formation thereofINTEL CORP·Filed 1998·Granted Dec 23, 2003·6 cites·17 claims
- 2638US6251762B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jun 26, 2001·5 cites·11 claims
- 2737US6271096B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Aug 7, 2001·2 cites·35 claims
- 2834US6268254B1Method and device for improved salicide resistance on polysilicon gatesINTEL CORP·Filed 1999·Granted Jul 31, 2001·1 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Steven J. Keating files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →