Inventor

WANG PING-CHUAN

US177 patents

⚠️ This page may combine multiple inventors who share the name “WANG PING-CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG PING-CHUAN

IBM

Process of enclosing via for improved reliability in dual damascene interconnects

Thermoelectric 3D cooling

Interconnect structure with bi-layer metal cap

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

Three-dimensional chip-stack synchronization

Gas dielectric structure forming methods

Micro-electro-mechanical RF switch

Methodology for recovery of hot carrier induced degradation in bipolar devices

On-chip semiconductor device having enhanced variability

E-fuse with hybrid metallization

On-chip structure for security application

Electronic fuse having a damaged region

Method of forming electronic fuse line with modified cap

Metal gate structures for CMOS transistor devices having reduced parasitic capacitance

Metal gate structures for CMOS transistor devices having reduced parasitic capacitance

Thermoelectric 3D cooling

Programmable through silicon via

Leakage current mitigation in a semiconductor device

Structures including means for lateral current carrying capability improvement in semiconductor devices

Programmable through silicon via

Method and apparatus for extending the lifetime of a semiconductor chip

Metal cap for interconnect structures

Empty vias for electromigration during electronic-fuse re-programming

Integration circuits for reducing electromigration effect

Method and apparatus to measure threshold shifting of a MOSFET device and voltage difference between nodes

Test structure for locating electromigration voids in dual damascene interconnects

Electromigration monitor

Structure of power grid for semiconductor devices and method of making the same

In-line depth measurement for thru silicon via

Method and apparatus for dynamic characterization of reliability wearout mechanisms

Method and apparatus for testing a micro electromechanical device

GLOBALFOUNDRIES INC

Integrated circuit (IC) test structure with monitor chain and test wires

Interconnect structures with variable dopant levels

Inducing device variation for security applications

Precision trench capacitor

FENG KAI D

Physical unclonable function cell and array

Method and apparatus for preventing circuit failure

On-chip accelerated failure indicator

FILIPPI RONALD G

Stacked via structure for metal fuse applications

Electromigration immune through-substrate vias

GLUSCHENKOV OLEG

Configurable interposer

DING HANYI

Test structure for determination of TSV depth

BONILLA GRISELDA

Interconnect structure for integrated circuits having enhanced electromigration resistance

HSU LOUIS L

Redundancy design with electro-migration immunity

YANG CHIH-CHAO

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

CHANDA KAUSHIK

Stress locking layer for reliable metallization

FENG KAI DI

3D chip-stack with fuse-type through silicon via

COOLBAUGH DOUGLAS D

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

WANG PING-CHUAN

Structure of metal e-fuse

HSU LOUIS LU-CHEN

Active inductor for ASIC application