Inventor

XU JEFFREY JUNHAO

TW65 patents

⚠️ This page may combine multiple inventors who share the name “XU JEFFREY JUNHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XU JEFFREY JUNHAO

QUALCOMM INC

Semiconductor device having a gap defined therein

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

Silicon germanium FinFET formation by Ge condensation

Integrated circuits including a FinFET and a nanostructure FET

Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)

Contact wrap around structure

Adjacent device isolation

Self-aligned structure

Intergrated circuit devices including an interfacial dipole layer

High dielectric constant/metal gate (HK/MG) compatible floating gate (FG)/ferroelectric dipole non-volatile memory

Integrated circuit devices and methods

Selective conductive barrier layer formation

Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC)

Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

Semiconductor device having an airgap defined at least partially by a protective structure

Nanowire device with reduced parasitics

Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods

Ferroelectric-modulated Schottky non-volatile memory

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Method and apparatus for selectively forming nitride caps on metal gate

Vertically stacked nanowire field effect transistors

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices

Minimum track standard cell circuits for reduced area

Method and apparatus of multi threshold voltage CMOS

Non-volatile one-time programmable memory device

Integrated circuit devices and methods

Middle-of-line integration methods and semiconductor devices

Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods

Non-volatile multiple time programmable memory device

Adjacent device isolation

Method and apparatus of stressed FIN NMOS FinFET

Method and apparatus of multi threshold voltage CMOS

Complementarily strained FinFET structure

Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC)

TAIWAN SEMICONDUCTOR MFG

FinFET/tri-gate channel doping for multiple threshold voltage tuning

Bottom-notched SiGe FinFET formation using condensation

FinFETs and methods for forming the same

Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce Schottky barrier

Methods for forming FinFETs with self-aligned source/drain

Methods for forming FinFETs having multiple threshold voltages

Pitch by splitting bottom metallization layer

Semiconductor device with a buried stressor

Shallow trench isolation corner rounding

TAIWAN SEMICONDUCTOR MFG CO LTD

FinFETs and methods for forming the same

FinFETs and methods for forming the same

FinFETs and methods for forming the same

CHANG CHIH-HAO

Bottom-notched SiGe FinFET formation using condensation

WU ZHIQIANG

Semiconductor device with a buried stressor

HUAWEI TECH CO LTD

Ferroelectric memory and storage device