Inventor

LEE HSIANG-HUAN

TW66 patents

⚠️ This page may combine multiple inventors who share the name “LEE HSIANG-HUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE HSIANG-HUAN

TAIWAN SEMICONDUCTOR MFG CO LTD

Lithography using high selectivity spacers for pitch reduction

Lithography using high selectivity spacers for pitch reduction

Lithography using multilayer spacer for reduced spacer footing

Via pre-fill on back-end-of-the-line interconnect layer

Copper etching integration scheme

Integrated circuit interconnects and methods of making same

Copper etching integration scheme

Back end of the line (BEOL) interconnect scheme

Method and apparatus for back end of line semiconductor device processing

Copper etching integration scheme

Interconnect structure and manufacturing method thereof

Method for forming interconnect structure that avoids via recess

Method for via plating with seed layer

Interconnect structures comprising flexible buffer layers

Interconnect structure including a continuous conductive body

Method of manufacturing a semiconductor device

Selective formation of conductor nanowires

Selective formation of conductor nanowires

Method of semiconductor integrated circuit fabrication

Method for via plating with seed layer

Via pre-fill on back-end-of-the-line interconnect layer

Method of manufacturing a semiconductor device

Selective formation of conductor nanowires

Method of semiconductor integrated circuit fabrication

Copper etching integration scheme

Method of semiconductor integrated circuit fabrication

TAIWAN SEMICONDUCTOR MFG

Lithography using high selectivity spacers for pitch reduction

Method of semiconductor integrated circuit fabrication

Dual damascene gap filling process

Interconnect structure and manufacturing method thereof

Method for forming interconnect structure that avoids via recess

Lithography using multilayer spacer for reduced spacer footing

Interconnect structures comprising flexible buffer layers

Copper etching integration scheme

Low resistance high reliability contact via and metal line structure for semiconductor device

Method and apparatus for back end of line semiconductor device processing

Semiconductor device metallization systems and methods

Interconnect having air gaps and polymer wrapped conductive lines

Method of semiconductor integrated circuit fabrication

Method for forming recess-free interconnect structure

Method of semiconductor integrated circuit fabrication

System and method for chemical-mechanical planarization of a metal layer

Interconnection wires of semiconductor devices

Interconnection wires of semiconductor devices

Method for via plating with seed layer

LU CHIH WEI

Method of semiconductor integrated circuit fabrication

LEE MING HAN

Copper etch scheme for copper interconnect structure

WU HSIEN-CHANG

Apparatus and method for low contact resistance carbon nanotube interconnect

TSAI CHENG-HSIUNG

Integrated circuit interconnects and methods of making same

LEE HSIANG-HUAN

Low resistance high reliability contact via and metal line structure for semiconductor device