Inventor

PAULSEN DAVID P

US90 patents

⚠️ This page may combine multiple inventors who share the name “PAULSEN DAVID P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAULSEN DAVID P

IBM

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low bower circuitry

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low power circuitry

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

3-D single gate inverter

Cognitive analysis using applied analog circuits

Method for low power operation and test using DRAM device

Generating a unique die identifier for an electronic chip

Implementing eFuse visual security of stored data using EDRAM

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Implementing eFuse visual security of stored data using EDRAM

Structure for metal oxide semiconductor capacitor

Precision IC resistor fabrication

Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications

Level-shifting latch

Level-shifting latch

Optimizing data approximation analysis using low power circuitry

Through-substrate via power gating and delivery bipolar transistor

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Method of implementing buried FET below and beside FinFET on bulk substrate

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Semiconductor chip with power gating through silicon vias

Implementing semiconductor soc with metal via gate node high performance stacked transistors

Real time cognitive reasoning using a circuit with varying confidence level alerts

Real time cognitive reasoning using a circuit with varying confidence level alerts

Sensing circuit for a non-volatile memory cell having two complementary memory transistors

Multiple-patterned semiconductor device channels

Signal path of a multiple-patterned semiconductor device

Method for correcting for asymmetry of threshold voltage shifts

Cognitive analysis using applied analog circuits

Real time cognitive monitoring of correlations between variables

Real time cognitive monitoring of correlations between variables

ERICKSON KARL R

eDRAM having dynamic retention and performance tradeoff

FinFET with body contact

Independently voltage controlled volume of silicon on a silicon on insulator chip

Vertically stacked FETs with series bipolar junction transistor

Implementing semiconductor SoC with metal via gate node high performance stacked transistors

Plural differential pair employing FinFET structure

Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit

Deep trench embedded gate transistor

CHER CHEN-YONG

Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components

Efficiency of static core turn-off in a system-on-a-chip with variation

GLOBALFOUNDRIES INC

Implementing eDRAM stacked FET structure

BARTLEY GERALD K

Through silicon via direct FET signal gating

PAONE PHIL C

Soft error detection

PAONE PHIL CHRISTOPHER FELICE

Method for creating 3-D single gate inverter