Inventor

SHEETS II JOHN E

US122 patents

⚠️ This page may combine multiple inventors who share the name “SHEETS II JOHN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEETS II JOHN E

IBM

High-density integrated circuit via capacitor

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low bower circuitry

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low power circuitry

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

3-D single gate inverter

False connection for defeating microchip exploitation

Power gating and clock gating in wiring levels

Cognitive analysis using applied analog circuits

Managed integrated circuit power supply distribution

Low resistance contact for transistors

Method for low power operation and test using DRAM device

Generating a unique die identifier for an electronic chip

Implementing eFuse visual security of stored data using EDRAM

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Implementing eFuse visual security of stored data using EDRAM

Decoupling capacitor using finFET topology

Structure for metal oxide semiconductor capacitor

Precision IC resistor fabrication

Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications

Charge-scaling multiplier circuit

Charge-scaling adder circuit

Metalization repair in semiconductor wafers

Metalization repair in semiconductor wafers

Optimizing data approximation analysis using low power circuitry

Low resistance contact for transistors

Through-substrate via power gating and delivery bipolar transistor

High-density integrated circuit via capacitor

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Method of implementing buried FET below and beside FinFET on bulk substrate

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Semiconductor chip with power gating through silicon vias

ERICKSON KARL R

eDRAM having dynamic retention and performance tradeoff

FinFET with body contact

Independently voltage controlled volume of silicon on a silicon on insulator chip

Vertically stacked FETs with series bipolar junction transistor

Implementing semiconductor SoC with metal via gate node high performance stacked transistors

BARTLEY GERALD K

Through silicon via direct FET signal gating

Field-effect transistor and method of creating same

Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies

Power domain controller with gated through silicon via having FET with horizontal channel

CHER CHEN-YONG

Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components

Efficiency of static core turn-off in a system-on-a-chip with variation

GLOBALFOUNDRIES INC

Implementing eDRAM stacked FET structure

CHRISTENSEN TODD A

Mask alignment, rotation and bias monitor utilizing threshold voltage dependence

PAONE PHIL C

Soft error detection