Inventor

EL-KAREH BADIH

US54 patents

⚠️ This page may combine multiple inventors who share the name “EL-KAREH BADIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EL-KAREH BADIH

IBM

Low voltage programmable storage element

Method for dual gate oxide dual workfunction CMOS

MOSFET with raised STI isolation self-aligned to the gate stack

Low voltage programmable storage element

Controlled dopant diffusion and metal contamination in thin polycide gate conductor of MOSFET device

Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack

Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device

Trench capacitor structures

Precision analog metal-metal capacitor

Precision analog metal-metal capacitor

Method of making flexible interconnections with dual-metal-dual-stud structure

ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up

Trench capacitor structures

Method of making a contact to a trench isolated device

Floating gate interlevel defect monitor and method

Buried field shield for an integrated circuit

Capacitor charging sensor

Flexible interconnections with dual-metal dual-stud structure

Method for electrostatic discharge protection through electric field emission

Method of fabricating a bipolar dynamic memory cell

Bipolar dynamic memory cell

High performance lateral PNP transistor with buried base contact

Method of forming high performance lateral PNP transistor with buried base contact

Bipolar two device dynamic memory cell

TEXAS INSTRUMENTS INC

Stacked capacitor and method for fabricating same

Stacked capacitor and method of fabricating same

Method for fabricating isolated integrated semiconductor structures

Open source/drain junction field effect transistor

Method of manufacturing an integrated circuit

Integrated BiCMOS semiconductor circuit

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

Method of producing complementary SiGe bipolar transistors

Method of fabricating complementary bipolar transistors with SiGe base regions

MICRON TECHNOLOGY INC

Fin-JFET

Fin-JFET

Methods of forming and programming memory devices with isolation structures

Buried decoupling capacitors, devices and systems including same, and methods of fabrication

Methods of forming memory devices with isolation structures

Systems, methods and devices for a memory having a buried select line

Vertically base-connected bipolar transistor

Vertically base-connected bipolar transistor

EL-KAREH BADIH

Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication

Vertically base-connected bipolar transistor

Buried decoupling capacitors, devices and systems including same, and methods of fabrication

Memory devices with isolation structures

Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors

Systems, methods and devices for a memory having a buried select line

Fin-JFET

TEXAS INSTRUMENTS DEUTSCHLAND

Silicide block isolated junction field effect transistor source, drain and gate

BALSTER SCOTT GERARD

High voltage bipolar transistor and method of fabrication