Fin-JFET

Abstract

Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a number of Fin-MOSFETs formed on a substrate; and 
 a number of Fin-JFETs formed on the substrate; 
 wherein a Fin structure associated with the number of Fin-JFETs has a width different than a width of a Fin structure associated with the number of Fin-MOSFETs. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the number of Fin-JFETs includes a number of nJFET devices and a number of pJFET devices having Fin structures formed according to a CMOS process. 
     
     
       3. The integrated circuit of  claim 1 , wherein the Fin structure associated with at least one of the number of Fin-JFETs has a greater width than the Fin structure associated with at least one of the number of Fin-MOSFETs. 
     
     
       4. The integrated circuit of  claim 1 , wherein the number of Fin-MOSFETs includes a number of NMOS FETs and a number of PMOS FETs having Fin structures formed according to a CMOS process. 
     
     
       5. The integrated circuit of  claim 1 , including:
 a dielectric material extending over the Fin structure associated with the number of Fin-JFET Fins and the Fin structure associated with the number of Fin-MOSFET Fins; and 
 a first conductive material extending over the Fin structures associated with the number of Fin-JFETs and the number of Fin-MOSFETs. 
 
     
     
       6. The integrated circuit of  claim 5 , including a second conductive material that forms at least one Fin-JFET terminal, wherein the second conductive material is doped differently than the first conductive material. 
     
     
       7. The integrated circuit of  claim 1 , wherein the number of Fin-MOSFETs and the number of Fin-JFETs have a quasi-planar topography. 
     
     
       8. An integrated circuit, comprising:
 at least one semiconductor Fin structure formed on a substrate; 
 a dielectric material formed over the at least one Fin structure, wherein portions of the dielectric material associated with a source, gate, and drain region of the Fin structure are selectively removed; 
 a first conductive material formed over the source and the drain regions; and 
 a second conductive material formed over the gate region; 
 wherein the second conductive material has a different type doping than the first conductive material. 
 
     
     
       9. The integrated circuit of  claim 8 , wherein the integrated circuit is a Fin-JFET device. 
     
     
       10. The integrated circuit of  claim 9 , wherein the at least one semiconductor Fin structure includes:
 a first number of semiconductor fins formed to a first set of dimensions; and 
 a second number of semiconductor fins formed to a second set of dimensions. 
 
     
     
       11. The integrated circuit of  claim 10 , wherein the first and second sets of dimensions have at least different drain-to-gate and source-to-gate spacing so as to achieve different Fin-JFET operating voltages and linearity. 
     
     
       12. An integrated circuit, comprising:
 at least one Fin-JFET on a substrate; 
 at least one Fin-MOSFET on the substrate; and 
 wherein fin structures for the at least one Fin-JFET and the at least one Fin-MOSFET are formed to substantially a same height out of a same semiconductor layer, and 
 wherein a Fin structure associated with the at least one Fin-JFET has a width different than a width of a Fin structure associated with the at least one Fin-MOSFET. 
 
     
     
       13. The integrated circuit of  claim 12 , wherein the quasi-planar topography includes:
 a gate conductive material contact landing pad recessed to a height not exceeding a source and drain height; and 
 areas between semiconductor structures filled with spacer dielectric material. 
 
     
     
       14. The integrated circuit of  claim 12 , wherein:
 Fin-MOSFET source and drain extensions are formed on a semiconductor Fin surface located furthest away from the substrate and adjacent to a gate dielectric material so as to reduce series resistance. 
 
     
     
       15. The integrated circuit of  claim 14 , including source and drain contacts formed on the semiconductor Fin surface located furthest away from the substrate. 
     
     
       16. The integrated circuit of  claim 12 , wherein the integrated circuit includes an analog circuit component including the at least one Fin-JFET. 
     
     
       17. The integrated circuit of  claim 16 , wherein the integrated circuit includes a digital component including the at least one Fin-MOSFET. 
     
     
       18. The integrated circuit of  claim 12 , wherein the at least one Fin-JFET and the at least one Fin-MOSFET are formed according to a CMOS process. 
     
     
       19. The integrated circuit of  claim 12 , wherein the integrated circuit is a system on a chip.