Inventor

CHUANG YI-LIN

TW49 patents

⚠️ This page may combine multiple inventors who share the name “CHUANG YI-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUANG YI-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Machine-learning design enablement platform

Cell layout of semiconductor device

Method and system for generating layout design of integrated circuit

Rule check violation prediction systems and methods

Static voltage drop (SIR) violation prediction systems and methods

Method for layout design and structure with inter-layer vias

Cell layout of semiconductor device

Machine-learning design enablement platform

Cell layout of semiconductor device

Method and system for generating layout design of integrated circuit

System and method for diagnosing design rule check violations

Hard-to-fix (HTF) design rule check (DRC) violations prediction

Circuit synthesis optimization for implements on integrated circuit

Rule check violation prediction systems and methods

Static voltage drop (SIR) violation prediction systems and methods

Hard-to-fix (HTF) design rule check (DRC) violations prediction

Circuit synthesis optimization for implements on integrated circuit

Static voltage drop (SIR) violation prediction systems and methods

Method and system for fixing violation of layout

Method for optimizing floor plan for an integrated circuit

Method and system for timing optimization with detour prediction

Cell layout of semiconductor device

Circuit synthesis optimization for implements on integrated circuit

Hard-to-fix (HTF) design rule check (DRC) violations prediction

Method of forming a semiconductor device with inter-layer vias

Rule check violation prediction systems and methods

Rule check violation prediction systems and methods

System and method for diagnosing design rule check violations

System for layout design of structure with inter layer vias

Method and system for generating layout design of integrated circuit

Post-routing congestion optimization

Method and system for fixing violation of layout

Method for optimizing floor plan for an integrated circuit

Method for optimizing floor plan for an integrated circuit

Post-routing congestion optimization

Static voltage drop (SIR) violation prediction systems and methods

Constraint determination system and method for semiconductor circuit

Method for displaying timing information of an integrated circuit floorplan in real time

Integrated circuit comprising buffer chain

Method for layout design and structure with inter-layer vias

Oxide definition (OD) gradient reduced semiconductor device

TAIWAN SEMICONDUCTOR MFG

Register clustering for clock network topology generation

Register clustering for clock network topology generation

Method for displaying timing information of an integrated circuit floorplan

Integrated circuit comprising buffer chain

Oxide definition (OD) gradient reduced semiconductor device and method of making

CHUANG YI-LIN

Group bounding box region-constrained placement for integrated circuit design

Methods and apparatus for floorplanning and routing co-design

Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs