Inventor

KALAFALA KERIM

US81 patents

⚠️ This page may combine multiple inventors who share the name “KALAFALA KERIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALAFALA KERIM

IBM

System and method for correlated process pessimism removal for static timing analysis

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

Leverage cycle stealing within optimization flows

Timing optimization driven by statistical sensitivites

Timing adjustments across transparent latches to facilitate power reduction

Dynamic voltage frequency scaling

Variable accuracy parameter modeling in statistical timing

System and method for maintaining slack continuity in incremental statistical timing analysis

Method for performing a parallel static timing analysis using thread-specific sub-graphs

Variable threshold system and method for multi-corner static timing analysis

Method of identifying paths with delays dominated by a particular factor

Affinity-based clustering of vectors for partitioning the columns of a matrix

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Method and system for efficient validation of clock skews during hierarchical static timing analysis

System and method for efficient analysis of point-to-point delay constraints in static timing

Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions

Method, computer program product, and apparatus for static timing with run-time reduction

Leverage cycle stealing within optimization flows

Leverage cycle stealing within optimization flows

Multi-sided variations for creating integrated circuits

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Efficient parallel processing of a network with conflict constraints between nodes

Integration of functional analysis and common path pessimism removal in static timing analysis

Integration of functional analysis and common path pessimism removal in static timing analysis

Incremental common path pessimism analysis

Parallel access to running electronic design automation (EDA) application

Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

Programmable clock division methodology with in-context frequency checking

Method and system for timing violations in a circuit

Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits

System and method for combined path tracing in static timing analysis

System and method for efficient statistical timing analysis of cycle time independent tests

System and method for efficient statistical timing analysis of cycle time independent tests

Scaling voltages in relation to die location

Method of identifying paths with delays dominated by a particular factor

Leverage cycle stealing within optimization flows

Efficient parallel processing of a network with conflict constraints between nodes

Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip

Affinity-based clustering of vectors for partitioning the columns of a matrix

Parameter ordering for multi-corner static timing analysis

Methods of optimizing timing of signals in an integrated circuit design using proxy slack values

KALAFALA KERIM

Method of measuring the impact of clock skew on slack during a statistical static timing analysis

System and method for performing static timing analysis in the presence of correlations between asserted arrival times

FOREMAN ERIC A

System and method for common history pessimism relief during static timing analysis

Device history based delay variation adjustment during static timing analysis

GLOBALFOUNDRIES INC

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

SINHA DEBJIT

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

LAVIN MARK A

Decentralized dynamically scheduled parallel static timing analysis