Inventor

TUNE ANDREW DAVID

GB55 patents

⚠️ This page may combine multiple inventors who share the name “TUNE ANDREW DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TUNE ANDREW DAVID

ADVANCED RISC MACH LTD

Access control in a data processing apparatus

Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols

Low latency bypass buffer

Data processing apparatus and method for arbitrating access to a shared resource

Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit

Interconnect and method of managing a snoop filter for an interconnect

Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit

Data coherency management

Arbitrating circuitry and method

Arbitrating and multiplexing circuitry

Enforcing ordering of snoop transactions in an interconnect for an integrated circuit

Increased throughput for writes to memory

Receiver based communication permission token allocation

Circuitry and method

Interconnection network for integrated circuit

Interconnection network for integrated circuit

Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave

Latency optimized eviction allocation for memories

Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain

Coherency control

Cache replacement control

Apparatus and method for buffered interconnect

Data processing

Data processing

Data access request specifying enable vector

Storage controller

Handling write requests for a data array

Data store and method of allocating data to the data store

Patrol scrubbing cycle for data storage circuitry

Method and apparatus for reduction of recurring cache misses

Arbitrating and multiplexing circuitry

Transaction response modification within interconnect circuitry

Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests

Burst read with flexible burst length for on-chip memory

Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location

Data processing apparatus and method for controlling a transfer of payload data over a communication channel

Switching device using buffering

Arbitration circuitry

Cache coherency

Cache coherency

Hazard checking control within interconnect circuitry

Parallel snoop and hazard checking with interconnect circuitry

Interconnect and method of operation of an interconnect for ordered write observation (OWO)

TUNE ANDREW DAVID

Operating parameter control for integrated circuit signal paths

Modelling dependencies in data traffic

Selecting between contending data packets to limit latency differences between sources

Arbitration circuity and method for arbitrating between a plurality of requests for access to a shared resource

MACE TIMOTHY CHARLES

Apparatus and method for controlling issuing of transaction requests

FEERO BRETT STANLEY

Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure

BRUCE ALISTAIR CRONE

Bus interconnect device and a data processing apparatus including such a bus interconnect device