Increased throughput for writes to memory

Abstract

A method for write operations to memory include starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuitry performing the aforementioned operations can also perform write operations for a single word in two clock cycles.

What is claimed is: 
     
       1. A method for write operations to memory, the method comprising:
 starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; 
 loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; 
 triggering the n words to be stored in the memory; and 
 closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. 
 
     
     
       2. The method of  claim 1 , wherein n=2 and the write operations for the writing of the two words are performed in three clock cycles such that the first word of the two words is loaded during the first clock cycle, a second word of the two words is loaded during a second clock cycle and the write operations close during a third clock cycle during which the two words are stored in the memory. 
     
     
       3. The method of  claim 1 , wherein write circuitry for the memory comprises a first write driver to a set of bitlines and a second write driver to the set of bitlines. 
     
     
       4. The method of  claim 3 , wherein the write circuitry further comprises:
 a first column select circuitry for selecting a particular bitline of the set of bitlines. 
 
     
     
       5. The method of  claim 4 , wherein the write circuitry further comprises:
 a second column select circuitry for selecting a corresponding particular bitline of the set of bitlines. 
 
     
     
       6. The method of  claim 1 , wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles such that the n words are stored during the final clock cycle. 
     
     
       7. The method of  claim 1 , wherein starting the write operations for the writing of n words in the same row is performed in response to receiving a signal indicative of a blast write, the method further comprising:
 receiving a signal indicative of a conventional write; and 
 in response to receiving the signal indicative of the conventional write, starting write operations for writing one word to the memory, whereby any word written in response to the signal indicative of the conventional write is written in two clock cycles. 
 
     
     
       8. The method of  claim 1 , wherein starting the write operations for the writing of n words in the same row further comprises precharging bitlines of the memory and turning on a wordline; and
 wherein closing the write operations for the writing of the n words comprises turning off the wordline and signals associated with the triggering of the n words to be stored in the memory. 
 
     
     
       9. The method of  claim 1 , wherein the memory is static random access memory (SRAM). 
     
     
       10. A memory circuitry, comprising:
 a wordline driver for a memory, the wordline driver coupled to receive an address and select a corresponding wordline for the memory; 
 write circuitry; and 
 a control circuit for operating the wordline driver and the write circuitry, wherein the control circuit directs the write circuitry to:
 start write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; 
 load one or more additional words of the n words, each during a corresponding one or more additional clock cycles; 
 trigger the n words to be stored in the memory; and 
 close the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. 
 
 
     
     
       11. The memory circuitry of  claim 10 , wherein n=2 and the write operations for the writing of the two words are performed in three cycles such that the first word of the two words is loaded during the first clock cycle, a second word of the two words is loaded during a second clock cycle and the write operations close during a third clock cycle during which the two words are stored in the memory. 
     
     
       12. The memory circuitry of  claim 10 , wherein the write circuitry comprises a first write driver to a set of bitlines and a second write driver to the set of bitlines. 
     
     
       13. The memory circuitry of  claim 12 , wherein the write circuitry further comprises a first column select circuitry for selecting a particular bitline of the set of bitlines. 
     
     
       14. The memory circuitry of  claim 13 , wherein the write circuitry further comprises a second column select circuitry for selecting a corresponding particular bitline of the set of bitlines, wherein the first word is written to one bitcell coupled to the particular bitline and an additional word of the one or more additional words is written to another bitcell coupled to the corresponding particular bitline. 
     
     
       15. The memory circuitry of  claim 12 , wherein the first write driver and the second write driver further comprise write assist circuitry for controlling a level of an internal voltage. 
     
     
       16. The memory circuitry of  claim 10 , wherein the n words are triggered to be concurrently stored in the memory during a last clock cycle of the corresponding one or more additional clock cycles such that the n words are stored during the final clock cycle. 
     
     
       17. The memory circuitry of  claim 10 , wherein the control circuit is coupled to receive a chip enable signal, a clock signal, a blast mode enable signal, an address signal and wherein the control circuit is coupled to output to the write circuitry a precharge signal and a write column select signal. 
     
     
       18. The memory circuitry of  claim 10 , wherein the memory circuitry is cache circuitry. 
     
     
       19. The memory circuitry of  claim 10 , wherein the memory is static random access memory (SRAM). 
     
     
       20. The memory circuitry of  claim 10 , wherein starting the write operations for the writing of n words in the same row is performed in response to receiving a signal indicative of a blast write, wherein the control circuit further directs the write circuitry to:
 receive a signal indicative of a conventional write; and 
 in response to the signal indicative of the conventional write, start write operations for writing one word to the memory, whereby any word written in response to the signal indicative of the conventional write is written in two clock cycles.