Inventor

PUCHNER HELMUT

US42 patents

⚠️ This page may combine multiple inventors who share the name “PUCHNER HELMUT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PUCHNER HELMUT

LSI LOGIC CORP

Silicon carbide CMOS channel

Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices

Silicon germanium CMOS channel

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same

Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting product

Shallow trench isolation structure for laser thermal processing

Process for forming high dielectric constant gate dielectric for integrated circuit structure

System to improve ser immunity and punchthrough

Method of fabricating an indium field implant for punchthrough protection in semiconductor devices

Well formation For CMOS devices integrated circuit structures

Reduced soft error rate (SER) construction for integrated circuit structures

Silicon germanium CMOS channel

Fabrication of metal contacts for deep-submicron technologies

Indium field implant for punchthrough protection in semiconductor devices

Depletion free polysilicon gate electrodes

Integrated circuit isolation system

Integrated circuit isolation system

Shallow junction formation

Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate

Shallow junction formation

CYPRESS SEMICONDUCTOR CORP

Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor

Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors

Electrostatic discharge protection device

CMOS embedded high voltage transistor

Non-volatile memory and method of operating the same

Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies

SONOS type stacks for nonvolatile charge trap memory devices and methods to form the same

SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same

Drain extended MOS transistor with increased breakdown voltage

High voltage diode

Memory cell array latchup prevention

High reliability non-volatile static random access memory devices, methods and systems

WALKER ANDREW

Capacitor triggered silicon controlled rectifier

Circuit with electrostatic discharge protection

Circuit with electrostatic discharge protection

Circuit with electrostatic discharge protection

PUCHNER HELMUT

SONOS type stacks for nonvolatile change trap memory devices and methods to form the same

Method and circuit for reducing degradation in a regulated circuit

ZAIN SUHAIL

High reliability non-volatile static random access memory devices, methods and systems

Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices

WALKER ANDREW J

Voltage protection device