P
US6977400B2ExpiredUtilityPatentIndex 84

Silicon germanium CMOS channel

Assignee: LSI LOGIC CORPPriority: Nov 28, 2000Filed: Feb 18, 2003Granted: Dec 20, 2005
Est. expiryNov 28, 2020(expired)· nominal 20-yr term from priority
Inventors:PUCHNER HELMUTGIUST GARY K
H10D 62/822H10D 30/751H10D 30/601H10D 30/0278Y10S438/933H10D 30/798
84
PatentIndex Score
15
Cited by
5
References
1
Claims

Abstract

A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal. Thus, standard materials for the spacer, such as silicon oxide or silicon nitride are not preferred for this application, because they tend to be transparent to the laser beam emissions.

Claims

exact text as granted — not AI-modified
1. A semiconductor device formed according to a method for fabricating a semiconducting device on a substrate, the improvement comprising the sequential steps of:
 forming a strained silicon germanium channel layer on the substrate, 
 forming a gate insulation layer on top of the strained silicon germanium channel layer at a temperature that does not exceed about eight hundred centigrade, 
 forming a gate electrode on top of the gate insulation layer, 
 patterning the gate electrode, 
 impregnating a low dose drain dopant into the substrate, 
 activating the low dose drain dopant with a first laser anneal that activates desired portions of the low dose drain dopant without relaxing and heating the strained silicon germanium channel layer disposed beneath the gate electrode, thereby limiting diffusion of the low dose drain dopant underneath the gate electrode, 
 impregnating a source-drain dopant into the substrate, and 
 activating the source-drain dopant with a second laser anneal that activates desired portions of the source-drain drain dopant without relaxing and heating the strained silicon germanium channel layer disposed beneath the gate electrode, thereby limiting diffusion of the source-drain drain dopant underneath the gate electrode.

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