Inventor

ZBICIAK JOSEPH RAYMOND MICHAEL

US48 patents

⚠️ This page may combine multiple inventors who share the name “ZBICIAK JOSEPH RAYMOND MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZBICIAK JOSEPH RAYMOND MICHAEL

TEXAS INSTRUMENTS INC

Tracking streaming engine vector predicates to control processor execution

Converting a stream of data using a lookaside buffer

Tracking streaming engine vector predicates to control processor execution

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Transposing a matrix using a streaming engine

Storage organization for transposing a matrix using a streaming engine

Converting a stream of data using a lookaside buffer

Lookahead priority collection to support priority elevation

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Tracking debug events from an autonomous module through a data pipeline

Mechanism to queue multiple streams to run on streaming engine

Lookahead priority collection to support priority elevation

Tracking streaming engine vector predicates to control processor execution

Converting a stream of data using a lookaside buffer

Lookahead priority collection to support priority elevation

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Cache preload operations using streaming engine

Cache management operations using streaming engine

Tracking streaming engine vector predicates to control processor execution

Cache preload operations using streaming engine

Cache management operations using streaming engine

Tracking debug events from an autonomous module through a data pipeline

Tracking debug events from an autonomous module through a data pipeline

Vector SIMD VLIW data path architecture

Cache preload operations using streaming engine

Converting a stream of data using a lookaside buffer

Vector SIMD VLIW data path architecture

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Software-hardware memory management modes

Forming constant extensions in the same execute packet in a VLIW processor

Cache management operations using streaming engine

Storage organization for transposing a matrix using a streaming engine

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Vector SIMD VLIW data path architecture

Software-hardware memory management modes

Method for forming constant extensions in the same execute packet in a VLIW processor

Vector SIMD VLIW data path architecture

Mechanism to queue multiple streams to run on streaming engine

Memory management unit that applies rules based on privilege identifier

Memory attribute sharing between differing cache levels of multilevel cache

TRAN JONATHAN SON HUNG

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

DAMODARAN RAGURAM

Memory attribute sharing between differing cache levels of multilevel cache

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

GOOGLE LLC

Logging pages accessed from I/O devices

Logging pages accessed from I/O devices

ZBICIAK JOSEPH RAYMOND MICHAEL

Priority based exception mechanism for multi-level cache controller

CHACHAD ABHIJEET ASHOK

Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU