Inventor

LIU CHIN-CHOU

TW88 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHIN-CHOU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHIN-CHOU

TAIWAN SEMICONDUCTOR MFG CO LTD

Layout design methodology for stacked devices

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same

Second semiconductor wafer attached to a first semiconductor wafer with a through hole connected to an inductor

Package structure and method for forming the same

Layout design methodology for stacked devices

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

Method for manufacturing a cell having pins and semiconductor device based on same

Heat dissipation structure including stacked chips surrounded by thermal interface material rings

Electromagnetic shielding metal-insulator-metal capacitor structure

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

Integrated circuit device with improved layout

Electromagnetic shielding metal-insulator-metal capacitor structure

Integrated antenna on interposer substrate

Method, system and computer program product for generating layout for semiconductor device

Interconnect structure and method for forming the same

Interconnect structure, semiconductor structure including interconnect structure and method for forming the same

Semiconductor device and method of manufacture

Semiconductor device with filler cell region, method of generating layout diagram and system for same

3D IC power grid

Integrated circuit device with improved layout

Cell region including portion of conductor of another cell region and semiconductor device include the same

Method for manufacturing a cell having pins and semiconductor device based on same

Integrated circuit device with improved layout

Semiconductor device including protruding conductor cell regions

Integrated circuit device with improved layout

Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same

Interconnect structure

Method and system for generating layout diagram including wiring arrangement

Through-silicon via in integrated circuit packaging

System and method for generating layout diagram including wiring arrangement

Heat dissipation structures for three-dimensional system on integrated chip structure

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

Layout design methodology for stacked devices

Method and system of forming integrated circuit

System for generating layout diagram including wiring arrangement

Method for generating layout diagram including wiring arrangement

Heat dissipation structures

TAIWAN SEMICONDUCTOR MFG

Method of making semiconductor device and a control system for performing the same

Method and apparatus for diagnosing an integrated circuit

Ultra high resolution timing measurement

(unassigned)

Connector for long-arm scissors

Structure of scissors for cutting grass

CHEN JI-JAN

Built-in self-test for interposer

CHEN CHIH-CHIA

Switched capacitor comparator circuit

TSENG NAN-HSIN

Methods for detecting defect connections between metal bumps

CHUANG YI-LIN

Group bounding box region-constrained placement for integrated circuit design

LAM TONG KIN

Method and apparatus for diagnosing an integrated circuit

WANG MILL-JER

Test probing structure

GOEL SANDEEP KUMAR

Interposers of 3-dimensional integrated circuit package systems and methods of designing the same