Ultra high resolution timing measurement

Abstract

An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.

1. An integrated circuit for high-resolution timing measurement, comprising:
 a delay pulse generator; 
 a first oscillator to generate a first clock with a first frequency; 
 a second oscillator to generate a second clock with a second frequency; 
 an oscillator tuner; 
 a sampling module; 
 a counter; 
 wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner is configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the sampling module is configured to sample the delayed pulse at the first frequency, the counter is configured to generate a digital counter value by counting a number of samples made by the sampling module, and the digital counter is configured to output a count value indicating a time width of the delayed pulse. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the sampling module is a D flip-flop. 
     
     
       3. The integrated circuit of  claim 1 , wherein the counter has also statistical computational capabilities for measuring data multiple times. 
     
     
       4. The integrated circuit of  claim 1 , wherein the digital counter is configured to shift out a count value from the counter to an outside circuit for further processing. 
     
     
       5. The integrated circuit of  claim 1 , wherein the second oscillator is a tunable ring oscillator. 
     
     
       6. The integrated circuit of  claim 5 , wherein the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is configured to add a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is configured to add. 
     
     
       7. The integrated circuit of  claim 6 , wherein each coarse tune stage comprising:
 a multiplexer; and 
 one or more inverters; 
 wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is connected directly to the multiplexer, and a control signal of the multiplexer can select one of the first input path and the second input path as an output. 
 
     
     
       8. The integrated circuit of  claim 6 , wherein each fine tune stage comprises:
 a first input path including a first inverter and a CMOS pass transistor gate; and 
 a second input path including a second inverter; 
 wherein the first input path and the second input path are connected in parallel to an output of the fine tune stage and a control signal can turn on the first input path. 
 
     
     
       9. The integrated circuit of  claim 6 , wherein the second time delay multiplied by a number of the fine tune stages is approximately the same as the first time delay. 
     
     
       10. The integrated circuit of  claim 1 , further comprising a reset module that can send a reset signal to at least one of the sampling module and the counter. 
     
     
       11. The integrated circuit of  claim 10 , further comprising a reset counter that counts the reset signal sent to the counter. 
     
     
       12. An integrated circuit for high-resolution timing measurement, comprising:
 a delay pulse generator; 
 a first oscillator to generate a first clock with a first frequency; 
 a second oscillator to generate a second clock with a second frequency; 
 an oscillator tuner; 
 a sampling module; 
 a counter; 
 wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner is configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the second oscillator is a tunable ring oscillator, the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is capable of adding a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is capable of adding, the sampling module is configured to sample the delayed pulse at the first frequency, the counter in configured to generate a digital counter value by counting a number of samples by the sampling module, and the digital counter is configured to output the a time width of the delayed pulse as the digital counter value. 
 
     
     
       13. The integrated circuit of  claim 12 , wherein the sampling module is a D flip-flop. 
     
     
       14. The integrated circuit of  claim 12 , wherein the counter has also statistical computational capabilities for measuring data multiple times. 
     
     
       15. The integrated circuit of  claim 12 , wherein each coarse tune stage comprising:
 a multiplexer; and 
 one or more inverters; 
 wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is also connected directly to the multiplexer, and a control signal of the multiplexer is capable of selecting one of the first input path and the second input path as an output. 
 
     
     
       16. The integrated circuit of  claim 12 , wherein each fine tune stage comprising:
 a first input path including a first inverter and a CMOS pass transistor gate; and 
 a second input path including a second inverter; 
 wherein the first input path and the second input path capable of being connected in parallel to an output of the fine tune stage and a control signal is capable of turning on the first input path. 
 
     
     
       17. The integrated circuit of  claim 12 , wherein the second time delay multiplied by a number of the fine tune stages is approximately the same as the first time delay. 
     
     
       18. An integrated circuit for high-resolution timing measurement, comprising:
 a delay pulse generator; 
 a first oscillator to generate a first clock with a first frequency; 
 a second oscillator to generate a second clock with a second frequency; 
 an oscillator tuner; 
 a sampling module; 
 a counter; and 
 a reset module that can send a reset signal to the sampling module and/or the counter; 
 wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner in configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the second oscillator is a tunable ring oscillator, the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is capable of adding a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is capable of adding, the sampling module is a D flip-flop and is configured to sample the delayed pulse at the first frequency, the counter is configured to generate a digital counter value by counting a number of samples by the sampling module, the counter has also statistical computational capabilities for measuring data multiple times, and the digital counter is configures to output a time width of the delayed pulse as the digital counter value. 
 
     
     
       19. The integrated circuit of  claim 18 , wherein each coarse tune stage comprises:
 a multiplexer; and 
 one or more inverters; 
 wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is also connected directly to the multiplexer, and a control signal of the multiplexer is capable of selecting one of the first input path and the second input path as an output. 
 
     
     
       20. The integrated circuit of  claim 18 , wherein each fine tune stage comprising:
 a first input path including a first inverter and a CMOS pass transistor gate; and 
 a second input path including a second inverter; 
 wherein the first input path and the second input path are connected in parallel to an output of the fine tune stage and a control signal is capable of turning on the first input path.