Inventor
AHMED SHAFQAT
US27 patents
⚠️ This page may combine multiple inventors who share the name “AHMED SHAFQAT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
10 patentsUS9378839B2Jun 28, 2016
Apparatus and methods including source gates
MICRON TECHNOLOGY INC15 citations92
US10783967B2Sep 22, 2020
Apparatus and methods including source gates
MICRON TECHNOLOGY INC3 citations84
US10170189B2Jan 1, 2019
Apparatus and methods including source gates
MICRON TECHNOLOGY INC5 citations84
US9779816B2Oct 3, 2017
Apparatus and methods including source gates
MICRON TECHNOLOGY INC9 citations84
US11211126B2Dec 28, 2021
Apparatus and methods including source gates
MICRON TECHNOLOGY INC2 citations73
US12148474B2Nov 19, 2024
Apparatus and methods including source gates
MICRON TECHNOLOGY INC0 citations62
US11029861B2Jun 8, 2021
Sense flags in a memory device
MICRON TECHNOLOGY INC0 citations62
US10409506B2Sep 10, 2019
Sense flags in a memory device
MICRON TECHNOLOGY INC0 citations52
US10126967B2Nov 13, 2018
Sense operation flags in a memory device
MICRON TECHNOLOGY INC0 citations52
US9519582B2Dec 13, 2016
Sense operation flags in a memory device
MICRON TECHNOLOGY INC0 citations52
INTEL CORP
7 patentsUS6911695B2Jun 28, 2005
Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
INTEL CORP25 citations92
US7566915B2Jul 28, 2009
Guard ring extension to prevent reliability failures
INTEL CORP25 citations89
US7968976B2Jun 28, 2011
Guard ring extension to prevent reliability failures
INTEL CORP7 citations81
US7920419B2Apr 5, 2011
Isolated P-well architecture for a memory device
INTEL CORP2 citations61
US11500446B2Nov 15, 2022
Reducing power consumption in nonvolatile memory due to standby leakage current
INTEL CORP1 citations60
US7972909B2Jul 5, 2011
Guard ring extension to prevent reliability failures
INTEL CORP2 citations59
US11322546B2May 3, 2022
Current delivery and spike mitigation in a memory cell array
INTEL CORP0 citations52
LSI LOGIC CORP
5 patentsUS6537923B1Mar 25, 2003
Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
LSI LOGIC CORP26 citations92
US6495881B1Dec 17, 2002
Programmable read only memory in CMOS process flow
LSI LOGIC CORP6 citations73
US6495419B1Dec 17, 2002
Nonvolatile memory in CMOS process flow
LSI LOGIC CORP8 citations73
US6338992B1Jan 15, 2002
Programmable read only memory in CMOS process flow
LSI LOGIC CORP7 citations73
US6482075B1Nov 19, 2002
Process for planarizing an isolation structure in a substrate
LSI LOGIC CORP0 citations41