Inventor
ZIMMERMAN DAVID J
US31 patents
⚠️ This page may combine multiple inventors who share the name “ZIMMERMAN DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
17 patentsUS9064560B2Jun 23, 2015
Interface for storage device access over memory bus
INTEL CORP20 citations92
US9476940B2Oct 25, 2016
Boundary scan chain for stacked memory
INTEL CORP5 citations84
US7644250B2Jan 5, 2010
Defining pin functionality at device power on
INTEL CORP14 citations84
US7519891B2Apr 14, 2009
IO self test method and apparatus for memory
INTEL CORP15 citations84
US7580465B2Aug 25, 2009
Low speed access to DRAM
INTEL CORP6 citations74
US11200176B2Dec 14, 2021
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
INTEL CORP2 citations73
US10719443B2Jul 21, 2020
Apparatus and method for implementing a multi-level memory hierarchy
INTEL CORP2 citations73
US10541009B2Jan 21, 2020
Write data mask for power reduction
INTEL CORP3 citations73
US10504591B2Dec 10, 2019
Adaptive configuration of non-volatile memory
INTEL CORP2 citations73
US10347354B2Jul 9, 2019
Boundary scan chain for stacked memory
INTEL CORP3 citations73
US10241912B2Mar 26, 2019
Apparatus and method for implementing a multi-level memory hierarchy
INTEL CORP2 citations73
US10025737B2Jul 17, 2018
Interface for storage device access over memory bus
INTEL CORP2 citations73
US9922725B2Mar 20, 2018
Integrated circuit defect detection and repair
INTEL CORP2 citations70
US9548137B2Jan 17, 2017
Integrated circuit defect detection and repair
INTEL CORP4 citations70
US10026475B2Jul 17, 2018
Adaptive configuration of non-volatile memory
INTEL CORP0 citations52
US9036718B2May 19, 2015
Low speed access to DRAM
INTEL CORP0 citations52
US9564245B2Feb 7, 2017
Integrated circuit defect detection and repair
INTEL CORP1 citations47
RAMANUJAN RAJ K
4 patentsUS9317429B2Apr 19, 2016
Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
RAMANUJAN RAJ K92 citations97
US9600416B2Mar 21, 2017
Apparatus and method for implementing a multi-level memory hierarchy
RAMANUJAN RAJ K23 citations93
US9418700B2Aug 16, 2016
Bad block management mechanism
RAMANUJAN RAJ K15 citations84
US10795823B2Oct 6, 2020
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
RAMANUJAN RAJ K3 citations73