Inventor

TSAI TSUNG CHE

TW42 patents

⚠️ This page may combine multiple inventors who share the name “TSAI TSUNG CHE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI TSUNG CHE

TAIWAN SEMICONDUCTOR MFG

N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)

Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching

Electrostatic discharge (ESD) guard ring protective structure

Diode structure compatible with FinFET process

Diode structure compatible with FinFET process

Electrostatic discharge protection

Semiconductor device with self-aligned interconnects

ESD devices comprising semiconductor fins

GLOBALFOUNDRIES SG PTE LTD

Electronic devices with tunable electrostatic discharge protection and methods for producing the same

Integrated circuit electrostatic discharge protection

Integrated circuits resistant to electrostatic discharge and methods for producing the same

ESD protection circuit and method of making the same

High voltage PNP using isolation for ESD and method for producing the same

Integrated circuits with electrostatic discharge protection and methods for producing the same

Integrated circuits having transistors with high holding voltage and methods of producing the same

Methods for an ESD protection circuit including a floating ESD node

GLOBALFOUNDRIES US INC

Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

Electrostatic discharge clamp structures

Diode triggered silicon controlled rectifier

Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

Diode triggered silicon controlled rectifier (SCR) with hybrid diodes

Electrostatic discharge device

Electrostatic discharge clamp structures

Bi-directional breakdown silicon controlled rectifiers

TAIWAN SEMICONDUCTOR MFG CO LTD

Diode string implementation for electrostatic discharge protection

Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching

Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection

Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching and the FinFETs thereof

N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)

Diode structure compatible with FinFET process

Diode string implementation for electrostatic discharge protection

GLOBALFOUNDRIES INC

Fin-based diode structures with a realigned feature layout

Vertical fin-type devices and methods

High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET) technology and method for producing the same

Silicon-controlled rectifiers with wells laterally isolated by trench isolation regions

Electrostatic discharge devices with reduced capacitance

MICRON TECHNOLOGY INC

Apparatuses and methods including patterns in scribe regions of semiconductor devices

Bump coplanarity for semiconductor device assembly and methods of manufacturing the same

Bump coplanarity for semiconductor device assembly and methods of manufacturing the same

LEE JAM-WEM

Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection

TSAI TSUNG-CHE

Electrostatic discharge (ESD) guard ring protective structure

CHIH YUE-DER

Semiconductor device with self-aligned interconnects