Apparatuses and methods including patterns in scribe regions of semiconductor devices

Abstract

Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.

What is claimed is: 
     
       1. An apparatus comprising:
 a first chip and a second chip; 
 a scribe region between the first chip and the second chip; and 
  a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; 
 wherein the apparatus includes, in the crack guide region, a first set of lines in a first insulating layer, a set of vias in the first insulating layer, a second set of lines in a second insulating layer, and a third set of lines in a third insulating layer, 
 wherein a first end of each via in the set of vias adjoins a first line of the first set of lines and a second end of each via in the set of vias adjoins a second line of the second set of lines, and 
 wherein no vias adjoin the third set of lines. 
 
     
     
       2. The apparatus of  claim 1 , wherein the scribe region further comprises a first pad region including at least one first test terminal of the first chip and a second pad region including at least one second test terminal of the second chip, and
 wherein a structure including the first set of lines, the set of vias and the second set of lines is disposed between the first and second pad regions. 
 
     
     
       3. The apparatus of  claim 1 , a structure including the first set of lines, the set of vias, and the second set of lines extends in a first direction parallel to the dicing line that is perpendicular to a second direction to the first chip. 
     
     
       4. The apparatus of  claim 1 , wherein the first set of lines, the set of vias, the second set of lines, or the third set of lines have a hardness greater than a hardness of the first insulating layer, the second insulating layer, or the third insulating layer. 
     
     
       5. The apparatus of  claim 4 , wherein the first insulating layer, the second insulating layer, or the third insulating layer comprises a low dielectric constant (low-k) material. 
     
     
       6. The apparatus of  claim 4 , wherein a structure including the first set of lines, the set of vias, and the second set of lines comprises metal. 
     
     
       7. The apparatus of  claim 1 , wherein a structure including the first set of lines, the set of vias, and the second set of lines extends across layers. 
     
     
       8. The apparatus of  claim 7 , wherein vias in the set of vias are connected to another pattern below the layers. 
     
     
       9. An apparatus comprising:
 a circuit region including at least one circuit; 
 at least one side surface; and 
 a circuit edge including a crack guide region extending along the side surface, 
 wherein the crack guide region comprises a first set of lines in a first insulating layer, a set of vias in the first insulating layer, a second set of lines in a second insulating layer, and a third set of lines in a third insulating layer, 
 wherein a first end of each via in the set of vias adjoins a first line of the first set of lines and a second end of each via in the set of vi as adjoins a second line of the second set of lines, and 
 wherein no vias adjoin the third set of lines. 
 
     
     
       10. The apparatus of  claim 9 , further comprising one or more cracks along the crack guide region. 
     
     
       11. The apparatus of  claim 10 , wherein a structure including the first set of lines, the set of vias, and the second set of lines is configured to be collapsed. 
     
     
       12. An apparatus comprising:
 a first chip and a second chip; and 
 a scribe region including a crack guide region between the first chip and the second chip; 
 wherein the apparatus includes, in the crack guide region, 
 a first set of lines in a first insulating layer, a set of vias in the first insulating layer, a second set of lines in a second insulating layer, and a third set of lines in a third insulating layer, 
 wherein a first end of each via in the set of vias adjoins a first line of the first set of lines and a second end of each via in the set of vias adjoins a second line of the second set of lines, and 
 wherein no vias adjoin the third set of lines. 
 
     
     
       13. The apparatus of  claim 12 , wherein a structure including the first set of lines, the set of vias, and the second set of lines is configured to collapse responsive to dicing. 
     
     
       14. The apparatus of  claim 12 , wherein a structure including the first set of lines, the set of vias, and the second set of lines is configured to guide a force in a dicing direction perpendicular to a, direction to the first chip. 
     
     
       15. The apparatus of  claim 12 , further comprising a crack mitigation structure at a side of a structure including the first set of lines, the set of vas, and the second set of lines, the crack mitigation structure being configured to guide a force to the center of the scribe region. 
     
     
       16. The apparatus of  claim 15 , wherein the crack mitigation structure comprises:
 one or more lines extending in a dicing direction; and 
 one or more line segments extending in a direction perpendicular to the dicing direction configured to guide a force to the center of the scribe region.