Inventor

DUTTA ASHIM

US87 patents

⚠️ This page may combine multiple inventors who share the name “DUTTA ASHIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUTTA ASHIM

IBM

Formation of embedded magnetic random-access memory devices

Pillar-based memory hardmask smoothing and stress reduction

Method of forming barrier free contact for metal interconnects

Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts

Lithographic alignment of a conductive line to a via

Forming self-aligned multi-metal interconnects

Embedded memory devices

Fully aligned via for interconnect

Forming self-aligned multi-metal interconnects

MRAM integration with BEOL interconnect including top via

Preserving underlying dielectric layer during MRAM device formation

Hardmask stress, grain, and structure engineering for advanced memory applications

Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication

MRAM device formation with in-situ encapsulation

Advanced metal interconnect

Layered bottom electrode dielectric for embedded MRAM

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

Fabrication of embedded memory devices utilizing a self assembled monolayer

Dual layer top contact for magnetic tunnel junction stack

Contact structure formation for memory devices

Contact structure formation for memory devices

MRAM cell embedded in a metal layer

Dielectric fill for tight pitch MRAM pillar array

High density two-tier MRAM structure

Subtractive top via as a bottom electrode contact for an embedded memory

Fabrication of embedded memory devices utilizing a self assembled monolayer

Multi-layer bottom electrode for embedded memory devices

Hardmask stress, grain, and structure engineering for advanced memory applications

Air gap in beol interconnect

Back-end-of-line thin film resistor

MRAM device with wrap-around top electrode

Additive interconnect formation

Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via

High-density resistive random-access memory array with self-aligned bottom electrode contact

Nonmetallic liner around a magnetic tunnel junction

Placing top vias at line ends by selective growth of via mask from line cut dielectric

Pillar-based memory hardmask smoothing and stress reduction

Selective encapsulation for metal electrodes of embedded memory devices

Embedded memory pillar

Inverse tone pillar printing method using organic planarizing layer pillars

Fabrication of back-end-of-line interconnects

EUV pattern transfer using graded hardmask

Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer

Embedding magneto-resistive random-access memory devices between metal levels

Method for fabricating a semiconductor device including self-aligned top via formation at line ends

Semiconductor structure with fully aligned vias

Placing top vias at line ends by selective growth of via mask from line cut dielectric

Inverse tone pillar printing method using polymer brush grafts

MICRON TECHNOLOGY INC

Semiconductor constructions

TOKYO ELECTRON LTD

Systems and methods for patterning features in tantalum nitride (TaN) layer