Inventor

LI MU-JING

US27 patents

⚠️ This page may combine multiple inventors who share the name “LI MU-JING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI MU-JING

SUN MICROSYSTEMS INC

Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout

Method and system for automating design rule check error correction in a CAD environment

Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout

Automated correction of asymmetric enclosure rule violations in a design layout

Method and system for ensuring consistency of design rule application in a CAD environment

Patching technique for correction of minimum area and jog design rule violations

Via enclosure rule check in a multi-wide object class design layout

Pure fill via area extraction in a multi-wide object class design layout

Redundant via rule check in a multi-wide object class design layout

(Design rule check)/(electrical rule check) algorithms using a system resolution

Automated design rule violation correction when adding dummy geometries to a design layout

Computer aided design flow to locate grounded fill in a large scale integrated circuit

Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules

Correction of spacing violations between pure fill via areas in a multi-wide object class design layout

Correction of width violations of dummy geometries

Method, system and computer product to produce a computer-generated integrated circuit design

Structure and method for separating geometries in a design layout into multi-wide object classes

Grounded fill in a large scale integrated circuit

Correction of spacing violations between dummy geometries and wide class objects of design geometries

Correction of spacing violations between wide class objects of dummy geometries

Method to simplify and speed up design rule/electrical rule checks

Correction of spacing violations between design geometries and wide class objects of dummy geometries

LI MU-JING

Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow

Power grid mosaicing with deep-sub-tile cells

Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow

ORACLE INT CORP

Dynamically generating jog patches for jog violations

Arraying power grid vias by tile cells