Correction of width violations of dummy geometries

Abstract

Automated techniques to correct certain rule violations with respect to non-design geometries are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. Correcting minimum width rule violations of non-design geometries is accomplished by forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry, and deducting the cutting areas form the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries. Any slivers of remaining non-design geometries, i.e., any pieces that are smaller than a minimum size amount, are removed. Cutting areas are formed by stretching ends of erroneous edge segments by a minimum width rule amount and sizing the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount.

1. A method for we in connection with a design layout of an electronic circuit, the design layout having non-design geometries, the method comprising:
 forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
   
   
     2. The method, as recited in  claim 1 , further comprising:
 removing any of the two or more remaining non-design geometries which are smaller than a minimum size amount, wherein the removing includes:  
 performing a sizing down operation utilizing a sizing factor on the two or more remaining non-design geometries, and  
 performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation.  
 
   
   
     3. The method, as recited in  claim 2 , wherein the sizing factor is slightly less than one half of the minimum size amount. 
   
   
     4. The method, as recited in  claim 1 , wherein the forming the one or more cutting areas comprises:
 identifying erroneous edge segments of the non-design geometry;  
 stretching ends of the erroneous edge segments by a minimum width rule amount forming stretched edges; and  
 sizing one or more of the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount forming the one or more cutting areas.  
 
   
   
     5. The method, as recited in  claim 4 , wherein the identifying the erroneous edge segments comprises:
 obtaining error marker geometries generated by an electronic design automation (EDA) tool on an erroneous non-design object geometry; and  
 using the error marker geometries to obtain the erroneous edge segments.  
 
   
   
     6. The method, as recited in  claim 1 , where the non-design geometry is a dummy geometry. 
   
   
     7. A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout having non-design geometries, the method comprising:
 forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
   
   
     8. The method, as recited in  claim 7 , further comprising:
 removing any of the two or more remaining non-design geometries which are smaller than a minimum size amount, wherein the removing includes: 
 performing a sizing down operation utilizing a sizing factor on the two or more remaining non-design geometries, and  
 performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation.  
 
 
   
   
     9. The method, as recited in  claim 8 , wherein the sizing factor is slightly less than one half of the minimum size amount. 
   
   
     10. The method, as recited in  claim 7 , wherein the forming the one or more cutting areas comprises:
 identifying erroneous edge segments of the non-design geometry;  
 stretching ends of the erroneous edge segments by a minimum width rule amount forming stretched edges; and  
 sizing one or more of the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount forming the one or more cutting areas.  
 
   
   
     11. The method, as recited in  claim 10 , wherein the identifying the erroneous edge segments comprises:
 obtaining error marker geometries generated by an electronic design automation (EDA) tool on an erroneous non-design object geometry; and  
 using the error marker geometries to obtain the erroneous edge segments.  
 
   
   
     12. The method, as recited in  claim 7 , where the non-design geometry is a dummy geometry. 
   
   
     13. An electronic circuit comprising:
 a plurality of non-design geometries;  
 wherein a design layout of the electronic circuit was generated by: 
 forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
 
   
   
     14. The electronic circuit, as recited in  claim 13 , wherein the design layout was further generated by:
 removing any of the two or more remaining non-design geometries which are smaller than a minimum size amount, wherein the removing includes: 
 performing a sizing down operation utilizing a sizing factor on the two or more remaining non-design geometries, and  
 performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation.  
 
 
   
   
     15. The electronic circuit, as recited in  claim 14 , wherein the sizing factor is slightly less than one half of die minimum size amount. 
   
   
     16. The electronic circuit, as recited in  claim 13 , wherein the forming the one or more cutting areas comprises:
 identifying erroneous edge segments of the non-design geometry;  
 stretching ends of the erroneous edge segments by a minimum width rule amount forming stretched edges; and  
 sizing one or more of the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount forming the one or more cutting areas.  
 
   
   
     17. The electronic circuit, as recited in  claim 16 , wherein the identifying the erroneous edge segments comprises:
 obtaining error marker geometries generated by an electronic design automation (EDA) tool on an erroneous non-design object geometry; and  
 using the error marker geometries to obtain the erroneous edge segments.  
 
   
   
     18. The electronic circuit, as recited in  claim 13 , where the non-design geometry is a dummy geometry. 
   
   
     19. A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:
 one or more design file media encoding representations of a plurality of non-design geometries;  
 wherein the computer readable encoding of the electronic circuit design was generated by: 
 forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
 
   
   
     20. The computer readable encoding, as recited in  claim 19 , wherein the computer readable encoding was further generated by:
 removing any of the two or more remaining non-design geometries which are smaller than a minimum size amount, wherein the removing includes: 
 performing a sizing down operation utilizing a sizing factor on the two or more remaining non-design geometries, and  
 performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation.  
 
 
   
   
     21. The computer readable encoding, as recited in  claim 20 , wherein the sizing factor is slightly less than one half of the minimum size amount. 
   
   
     22. The computer readable encoding, as recited in  claim 19 , wherein the forming the one or more cutting areas comprises:
 identifying erroneous edge segments of the non-design geometry;  
 stretching ends of the erroneous edge segments by a minimum width rule amount forming stretched edges; and  
 sizing one or more of the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount forming the one or more cutting areas.  
 
   
   
     23. The computer readable encoding, as recited in  claim 22 , wherein the identifying the erroneous edge segments comprises:
 obtaining error marker geometries generated by an electronic design automation (EDA) tool on an erroneous non-design object geometry; and  
 using the error marker geometries to obtain the erroneous edge segments.  
 
   
   
     24. The computer readable encoding, as recited in  claim 19 , where the non-design geometry is a dummy geometry. 
   
   
     25. An apparatus comprising:
 means for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout having non-design geometries, the means for processing comprising: 
 means for forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 means for deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
 
   
   
     26. The apparatus, as recited in  claim 25 , the means for processing further comprising:
 means for removing any of the two or more remaining non-design geometries which are smaller than a minimum size amount, wherein the means for removing includes: 
 means for performing a sizing down operation utilizing a sizing factor on the two or more remaining non-design geometries, and  
 means for performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation.  
 
 
   
   
     27. The apparatus, as recited in  claim 26 , wherein the sizing factor is slightly less than one half of the minimum size mount. 
   
   
     28. The apparatus, as recited in  claim 25 , wherein the means for forming the one or more cutting areas comprises:
 means for identifying erroneous edge segments of the non-design geometry;  
 means for stretching ends of the erroneous edge segments by a minimum width rule amount forming stretched edges; and  
 means for sizing one or more of the stretched edge segments which are inside the non-design geometry outward by a minimum spacing rule amount forming the one or more cutting areas.  
 
   
   
     29. The apparatus, as recited in  claim 28 , wherein the means for identifying the erroneous edge segments comprises:
 means for obtaining error marker geometries generated by an electronic design automation (EDA) tool on an erroneous non-design object geometry; and  
 means for using the error marker geometries to obtain the erroneous edge segments.  
 
   
   
     30. The apparatus, as recited in  claim 25 , where the non-design geometry is a dummy geometry. 
   
   
     31. A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, the design layout having non-design geometries, the method comprising:
 forming one or more cutting areas adjoining one or more erroneous edges of a non-design geometry; and  
 deducting the one or more cutting areas from the non-design geometry, splitting the non-design geometry into two or more remaining non-design geometries.  
 
   
   
     32. The method, as recited in  claim 31 , wherein the computer readable media product is embodied as one or more media selected from the set of a disk, tape, or other magnetic, optical, semiconductor or electronic storage medium and a network, wire line, wireless or other communications medium.