Inventor

DIAZ CARLOS H

US258 patents

⚠️ This page may combine multiple inventors who share the name “DIAZ CARLOS H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIAZ CARLOS H

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-gate device and method of fabrication thereof

Horizontal gate-all-around device having wrapped-around source and drain

Non-volatile memory device having nanocrystal floating gate and method of fabricating same

Multi-gate device and method of fabrication thereof

Method of forming semiconductor structure with horizontal gate all around structure

Multi-gate device and method of fabrication thereof

Semiconductor devices and methods of manufacture thereof

Negative capacitance FET with improved reliability performance

Multi-gate semiconductor device and method for forming the same

Silicon and silicon germanium nanowire formation

Conformal source and drain contacts for multi-gate field effect transistors

Self-aligned wrapped-around structure

Semiconductor device and channel structure thereof

Silicon and silicon germanium nanowire formation

Contacts for highly scaled transistors

Silicon and silicon germanium nanowire formation

Horizontal gate-all-around device having wrapped-around source and drain

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

3D cross-bar nonvolatile memory

Structure and method for FinFET device with buried sige oxide

Contacts for highly scaled transistors

Memory device, semiconductor device, and method of fabricating semiconductor device

Contacts for highly scaled transistors

Silicon and silicon germanium nanowire formation

Nanowire stack GAA device with inner spacer and methods for producing the same

Contacts for highly scaled transistors

Semiconductor liner of semiconductor device

3D cross-bar nonvolatile memory

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Conformal source and drain contacts for multi-gate field effect transistors

TAIWAN SEMICONDUCTOR MFG

Self-aligned wrapped-around structure

Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane

Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same

Silicon and silicon germanium nanowire formation

Fin structure of semiconductor device

Tunnel field-effect transistors with superlattice channels

Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect

Structure and method for SRAM FinFET device

Tuning strain in semiconductor devices

Silicon-on-insulator ULSI devices with multiple silicon film thicknesses

Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions

Method for fabricating a shallow ion implanted microelectronic structure

Ultra-shallow junction formation by novel process sequence for PMOSFET

Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects

Formation of shallow trench isolation (STI)

TEXAS INSTRUMENTS INC

Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

ESD/EOS protection circuits for integrated circuits

Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit

HEWLETT PACKARD CO

Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies

Hot plug tolerant ESD protection for an IC