Silicon and silicon germanium nanowire formation

Abstract

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

What is claimed is: 
     
       1. A method for forming a semiconductor arrangement, comprising:
 forming a first silicon and silicon germanium stack over a substrate, the first silicon and silicon germanium stack comprising a first silicon layer and a first silicon germanium layer; 
 forming a first source region adjacent to a first side of the first silicon and silicon germanium stack; 
 forming a first drain region adjacent to a second side of the first silicon and silicon germanium stack; 
 oxidizing the first silicon and silicon germanium stack forming a first germanium nanowire channel, the oxidizing comprising transforming the first silicon layer and silicon of the first silicon germanium layer into a silicon oxide region, the first germanium nanowire channel formed between the first source region and the first drain region; 
 removing the silicon oxide region; 
 forming a first gate structure around the first germanium nanowire channel forming a first nanowire transistor; and 
 forming a second nanowire transistor comprising a first silicon nanowire channel. 
 
     
     
       2. The method of  claim 1 , the forming the second nanowire transistor comprising:
 forming a second silicon and silicon germanium stack over the substrate, the second silicon and silicon germanium stack comprising a second silicon layer and a second silicon germanium layer; 
 forming a second source region adjacent to a first side of the second silicon and silicon germanium stack; 
 forming a second drain region adjacent to a second side of the second silicon and silicon germanium stack; 
 removing the second silicon germanium layer from the second silicon and silicon germanium stack forming the first silicon nanowire channel, the first silicon nanowire channel formed between the second source region and the second drain region; and 
 forming a second gate structure around the first silicon nanowire channel forming the second nanowire transistor. 
 
     
     
       3. The method of  claim 1 , comprising:
 forming a second germanium nanowire channel, within the first nanowire transistor, from the first silicon and silicon germanium stack. 
 
     
     
       4. The method of  claim 2 , comprising:
 forming a second silicon nanowire channel, within the second nanowire transistor, from the second silicon and silicon germanium stack. 
 
     
     
       5. The method of  claim 1 , comprising:
 forming the first nanowire transistor as a PMOS transistor and the second nanowire transistor as an NMOS transistor during a single fabrication process. 
 
     
     
       6. The method of  claim 1 , the oxidizing the first silicon and silicon germanium stack comprising:
 removing a sacrificial gate formed over the first silicon and silicon germanium stack exposing the first silicon and silicon germanium stack to oxygen. 
 
     
     
       7. The method of  claim 1 , comprising:
 forming an interfacial layer between the first germanium nanowire channel and the first gate structure. 
 
     
     
       8. The method of  claim 1 , comprising:
 forming a high k dielectric layer between the first germanium nanowire channel and the first gate structure. 
 
     
     
       9. The method of  claim 2 , the removing the second silicon germanium layer comprising at least one of:
 performing an oxidation technique exposing the second silicon layer to oxygen forming the first silicon nanowire channel; or 
 performing a hydrogen annealing technique upon the second silicon layer forming the first silicon nanowire channel. 
 
     
     
       10. A method for forming a semiconductor arrangement, comprising:
 forming a first stack comprising a first layer having a first composition and a second layer having a second composition different than the first composition and a second stack comprising a third layer having the first composition and a fourth layer having the second composition; 
 applying a first mask over the second stack; 
 etching the first stack while the second stack is masked removing the first layer and forming a first nanowire channel; 
 forming a first gate structure around the first nanowire channel; 
 removing the first mask; 
 applying a second mask over the first stack; 
 etching the second stack while the first stack is masked removing the fourth layer and forming a second nanowire channel; and 
 forming a second gate structure around the second nanowire channel. 
 
     
     
       11. The method of  claim 10 , the first layer and the third layer comprising silicon. 
     
     
       12. The method of  claim 11 , the second layer and the fourth layer comprising silicon germanium. 
     
     
       13. The method of  claim 11 , comprising, prior to the etching the first stack:
 applying oxygen to the first stack oxidizing the first stack. 
 
     
     
       14. The method of  claim 10 , comprising, prior to the forming the first gate structure:
 forming an interfacial layer around the first nanowire channel. 
 
     
     
       15. The method of  claim 14 , comprising, prior to the forming the first gate structure:
 forming a high k dielectric layer around the interfacial layer. 
 
     
     
       16. The method of  10 , comprising, prior to the forming the second gate structure:
 applying oxygen to the second nanowire channel oxidizing the second nanowire channel. 
 
     
     
       17. The method of  claim 16 , comprising:
 annealing the second nanowire channel, after being oxidized, smoothing the second nanowire channel. 
 
     
     
       18. The method of  claim 10 , comprising, prior to the forming the second gate structure:
 forming an interfacial layer around the second nanowire channel. 
 
     
     
       19. A method for forming a semiconductor arrangement, comprising:
 forming a first stack comprising a first layer comprising silicon and a second layer comprising silicon germanium and a second stack comprising a third layer comprising silicon and a fourth layer comprising silicon germanium; 
 applying a first mask over the second stack; 
 applying oxygen to the first stack while the second stack is masked oxidizing the first stack; 
 etching the first stack, after being oxidized and while the second stack is masked, removing the first layer, the second layer forming a first nanowire channel; 
 forming a first gate structure around the first nanowire channel; 
 removing the first mask; 
 applying a second mask over the second stack; 
 etching the second stack while the first stack is masked removing the fourth layer, the third layer forming a second nanowire channel; and 
 forming a second gate structure around the second nanowire channel. 
 
     
     
       20. The method of  claim 19 , comprising:
 applying oxygen to the second nanowire channel while the second stack is masked oxidizing the second nanowire channel.