Inventor
NARAYANA PIDUGU L
US27 patents
Patents
27 patentsUS5852748ADec 22, 1998
Programmable read-write word line equality signal generation for FIFOs
CYPRESS SEMICONDUCTOR CORP20 citations92
US5712992AJan 27, 1998
State machine design for generating empty and full flags in an asynchronous FIFO
CYPRESS SEMICONDUCTOR CORP21 citations92
US5627797AMay 6, 1997
Full and empty flag generator for synchronous FIFOS
CYPRESS SEMICONDUCTOR CORP21 citations92
US6628171B1Sep 30, 2003
Method, architecture and circuit for controlling and/or operating an oscillator
CYPRESS SEMICONDUCTOR CORP21 citations91
US6400642B1Jun 4, 2002
Memory architecture
CYPRESS SEMICONDUCTOR CORP19 citations91
US6177843B1Jan 23, 2001
Oscillator circuit controlled by programmable logic
CYPRESS SEMICONDUCTOR CORP29 citations91
US6240031B1May 29, 2001
Memory architecture
CYPRESS SEMICONDUCTOR CORP18 citations82
US5850568ADec 15, 1998
Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness
CYPRESS SEMICONDUCTOR CORP16 citations82
US6675336B1Jan 6, 2004
Distributed test architecture for multiport RAMs or other circuitry
CYPRESS SEMICONDUCTOR CORP16 citations80
US6377071B1Apr 23, 2002
Composite flag generation for DDR FIFOs
CYPRESS SEMICONDUCTOR CORP13 citations74
US6070203AMay 30, 2000
Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS
CYPRESS SEMICONDUCTOR CORP10 citations74
US5994920ANov 30, 1999
Half-full flag generator for synchronous FIFOs
CYPRESS SEMICONDUCTOR CORP5 citations74
US5963056AOct 5, 1999
Full and empty flag generator for synchronous FIFOs
CYPRESS SEMICONDUCTOR CORP7 citations74
US5955897ASep 21, 1999
Signal generation decoder circuit and method
CYPRESS SEMICONDUCTOR CORP6 citations74
US5809339ASep 15, 1998
State machine design for generating half-full and half-empty flags in an asynchronous FIFO
CYPRESS SEMICONDUCTOR CORP11 citations74
US5661418AAug 26, 1997
Signal generation decoder circuit and method
CYPRESS SEMICONDUCTOR CORP8 citations74
US5860160AJan 12, 1999
High speed FIFO mark and retransmit scheme using latches and precharge
CYPRESS SEMICONDUCTOR CORP7 citations73
US6526470B1Feb 25, 2003
Fifo bus-sizing, bus-matching datapath architecture
CYPRESS SEMICONDUCTOR CORP10 citations71
US6016403AJan 18, 2000
State machine design for generating empty and full flags in an asynchronous FIFO
CYPRESS SEMICONDUCTOR CORP4 citations63
US5991834ANov 23, 1999
State machine design for generating half-full and half-empty flags in an asynchronous FIFO
CYPRESS SEMICONDUCTOR CORP5 citations63
US5844423ADec 1, 1998
Half-full flag generator for synchronous FIFOs
CYPRESS SEMICONDUCTOR CORP4 citations63
US6366979B1Apr 2, 2002
Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO
CYPRESS SEMICONDUCTOR CORP4 citations62
US6023435AFeb 8, 2000
Staggered bitline precharge scheme
CYPRESS SEMICONDUCTOR CORP6 citations61
US6489805B1Dec 3, 2002
Circuits, architectures, and methods for generating a periodic signal in a memory
CYPRESS SEMICONDUCTOR CORP2 citations60
US6055177AApr 25, 2000
Memory cell
CYPRESS SEMICONDUCTOR CORP2 citations59
US6292013B1Sep 18, 2001
Column redundancy scheme for bus-matching fifos
CYPRESS SEMICONDUCTOR CORP5 citations58
US6907539B1Jun 14, 2005
Configurage data setup/hold timing circuit with user programmable delay
CYPRESS SEMICONDUCTOR CORP0 citations28