Inventor
STARR GREGORY
US37 patents
⚠️ This page may combine multiple inventors who share the name “STARR GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
30 patentsUS6556044B2Apr 29, 2003
Programmable logic device including multipliers and configurations thereof to reduce resource utilization
ALTERA CORP233 citations99
US6538470B1Mar 25, 2003
Devices and methods with programmable logic and digital signal processing regions
ALTERA CORP318 citations99
US7346644B1Mar 18, 2008
Devices and methods with programmable logic and digital signal processing regions
ALTERA CORP101 citations98
US6771094B1Aug 3, 2004
Devices and methods with programmable logic and digital signal processing regions
ALTERA CORP67 citations96
US7075365B1Jul 11, 2006
Configurable clock network for programmable logic device
ALTERA CORP24 citations95
US7698358B1Apr 13, 2010
Programmable logic device with specialized functional block
ALTERA CORP33 citations92
US7216139B2May 8, 2007
Programmable logic device including multipliers and configurations thereof to reduce resource utilization
ALTERA CORP15 citations92
US7142010B2Nov 28, 2006
Programmable logic device including multipliers and configurations thereof to reduce resource utilization
ALTERA CORP21 citations92
US7119576B1Oct 10, 2006
Devices and methods with programmable logic and digital signal processing regions
ALTERA CORP46 citations92
US6924678B2Aug 2, 2005
Programmable phase-locked loop circuitry for programmable logic device
ALTERA CORP21 citations92
US6832173B1Dec 14, 2004
Testing circuit and method for phase-locked loop
ALTERA CORP24 citations92
US7193443B1Mar 20, 2007
Differential output buffer with super size
ALTERA CORP23 citations91
US7180334B2Feb 20, 2007
Apparatus and method for decreasing the lock time of a lock loop circuit
ALTERA CORP11 citations84
US7019570B2Mar 28, 2006
Dual-gain loop circuitry for programmable logic device
ALTERA CORP16 citations84
US7453968B2Nov 18, 2008
Dynamic phase alignment methods and apparatus
ALTERA CORP9 citations83
US7437401B2Oct 14, 2008
Multiplier-accumulator block mode splitting
ALTERA CORP12 citations83
US7286007B1Oct 23, 2007
Configurable clock network for programmable logic device
ALTERA CORP9 citations81
US7071743B2Jul 4, 2006
Programmable phase-locked loop circuitry for programmable logic device
ALTERA CORP8 citations74
US6958624B1Oct 25, 2005
Data latch with low-power bypass mode
ALTERA CORP6 citations74
US6586966B1Jul 1, 2003
Data latch with low-power bypass mode
ALTERA CORP5 citations74
US7859329B1Dec 28, 2010
Configurable clock network for programmable logic device
ALTERA CORP6 citations72
US7646237B1Jan 12, 2010
Configurable clock network for programmable logic device
ALTERA CORP6 citations72
US7307459B2Dec 11, 2007
Programmable phase-locked loop circuitry for programmable logic device
ALTERA CORP3 citations63
US6937062B1Aug 30, 2005
Specialized programmable logic region with low-power mode
ALTERA CORP2 citations63
US6566906B1May 20, 2003
Specialized programmable logic region with low-power mode
ALTERA CORP5 citations63
US7623609B2Nov 24, 2009
Dynamic phase alignment methods and apparatus
ALTERA CORP4 citations62
US8364738B1Jan 29, 2013
Programmable logic device with specialized functional block
ALTERA CORP0 citations52
US6714042B1Mar 30, 2004
Specialized programmable logic region with low-power mode
ALTERA CORP0 citations52
US9490812B1Nov 8, 2016
Configurable clock network for programmable logic device
ALTERA CORP0 citations51
US8680913B1Mar 25, 2014
Configurable clock network for programmable logic device
ALTERA CORP0 citations51
STARR GREGORY
3 patentsUS8441314B1May 14, 2013
Configurable clock network for programmable logic device
STARR GREGORY4 citations71
US8253484B1Aug 28, 2012
Configurable clock network for programmable logic device
STARR GREGORY3 citations71
US8072260B1Dec 6, 2011
Configurable clock network for programmable logic device
STARR GREGORY4 citations71