Devices and methods with programmable logic and digital signal processing regions

Abstract

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

What is claimed is: 
     
       1. A programmable logic device comprising:
 a plurality of programmable logic regions; 
 a digital signal processing region having a plurality of configurable modes of operation, the digital signal processing region comprising:
 a plurality of multiplier circuits that each have a multiplier output, and 
 a digital signal processing circuit dedicated to receiving one or more of the multiplier outputs and comprising circuitry that applies a particular digital signal processing operation to the received multiplier outputs depending on a selected mode of operation; and 
 interconnect resources that interconnect the digital signal processing region to at least some of the programmable logic regions. 
 
 
     
     
       2. The programmable logic device of  claim 1  wherein the digital processing circuit comprises:
 at least one add-subtract-accumulate circuit that is operative to receive the multiplier outputs; and 
 at least one add-subtract circuit that is operative to receive an output from the add-subtract-accumulate circuit. 
 
     
     
       3. The programmable logic device of  claim 1  wherein the digital processing circuit comprises:
 at least one first add-subtract circuit that is operative to receive the multiplier outputs; 
 at least one accumulate circuit that is operative to receive the multiplier outputs; and 
 at least one second add-subtract circuit that is operative to receive an output from the first add-subtract circuit. 
 
     
     
       4. The programmable logic device of  claim 2  wherein the add-subtract-accumulate circuit is operative to perform a selected computation based on the multiplier outputs and that depends on the selected mode of operation, the computation comprising one of addition, subtraction, and accumulation. 
     
     
       5. The programmable logic device of  claim 2  wherein the add-subtract-accumulate circuit is operative to output the multiplier outputs without performing an operation on the multiplier outputs. 
     
     
       6. The programmable logic device of  claim 2  wherein the add-subtract circuit is operative to perform a selected computation based on outputs from at least two of the add-subtract-accumulate circuits and that depends on the selected mode of operation, the computation comprising one of addition and subtraction. 
     
     
       7. The programmable logic device of  claim 2  wherein the add-subtract circuit is operative to perform two selected computations based on outputs from at least two of the add-subtract-accumulate circuits and that depends on the selected mode of operation, the two selected computations consisting of addition and subtraction. 
     
     
       8. The programmable logic device of  claim 2  wherein the add-subtract circuit is operative to output the output from the add-subtract-accumulate circuit without performing an operation on the add-subtract-accumulate circuit output. 
     
     
       9. The programmable logic device of  claim 1  wherein the digital signal processing region further comprises input register circuits that feed the plurality of multiplier circuits. 
     
     
       10. The programmable logic device of  claim 9  wherein the input register circuits are arranged as a scan chain. 
     
     
       11. The programmable logic device of  claim 10  wherein the scan chain is used to perform FIR filtering. 
     
     
       12. The programmable logic device of  claim 9  further comprising means for dynamically or statically programming inputs to at least one of the input registers to be logically inverted. 
     
     
       13. The programmable logic device of  claim 9  further comprising means for dynamically or statically programming a subset of input bits to at least one of the input registers to be logically inverted, wherein the subset of input bits corresponds to unused bits by the multiplier circuits. 
     
     
       14. The programmable logic device of  claim 2  further comprising:
 a pipeline register that is operative to receive an output from the add-subtract-accumulate circuit or the add-subtract circuit, wherein the pipeline register is internal or external to the digital signal processing region. 
 
     
     
       15. The programmable logic device of  claim 2  wherein the add-subtract-accumulate circuit comprises:
 at least one adder circuit; and 
 at least one programmable logic connector coupled to the adder circuit, wherein the programmable logic connector is statically or dynamically programmed to configure the adder circuit to perform the selected computation. 
 
     
     
       16. The programmable logic device of  claim 15  wherein the add-subtract-accumulate circuit comprises two adder circuits, wherein the first adder circuit is operative to perform an accumulation operation on lower order input bits of a selected multiplier output, and the second adder circuit is operative to perform the accumulation operation on higher order bits of the selected multiplier output. 
     
     
       17. The programmable logic device of  claim 16  wherein the add-subtract-accumulate circuit generates an overflow bit for the accumulation operation. 
     
     
       18. The programmable logic device of  claim 16  wherein the add-subtract-accumulate circuit further comprises a zeroing circuit coupled to the first adder circuit and to the second adder circuit for resetting the add-subtract-accumulate circuit when the selected computation is an accumulation operation. 
     
     
       19. The programmable logic device of  claim 18  wherein the zeroing circuit consists of an AND gate. 
     
     
       20. The programmable logic device of  claim 18  wherein resetting the add-subtract-accumulate circuit using the zeroing circuit consumes one clock cycle of a clock signal that is input to the digital signal processing region. 
     
     
       21. The programmable logic device of  claim 16  wherein an output register that receives the output of the add-subtract-accumulate circuit and that generates an output that is coupled to the first adder circuit and the second adder circuit is operative to receive a clear signal for resetting the add-subtract-accumulate circuit when the selected computation is an accumulation operation. 
     
     
       22. The programmable logic device of  claim 20  wherein resetting the add-subtract-accumulate circuit using the zeroing circuit consumes two clock cycles of a clock signal that is input to the digital signal processing region. 
     
     
       23. The programmable logic device of  claim 2  wherein the add-subtract-accumulate circuit further comprises means for generating a signed or unsigned output. 
     
     
       24. The programmable logic device of  claim 2  wherein the add-subtract-accumulate circuit is configurable to sign extend the received multiplier outputs. 
     
     
       25. The programmable logic device of  claim 2  wherein at least two outputs from input registers to the digital signal processing circuit are cross connected with at least two inputs to the multiplier circuits, or wherein at least two outputs of the multiplier circuits are cross connected with at least two inputs to the add-subtract-accumulate circuits. 
     
     
       26. The programmable logic device of  claim 1  wherein the multiplier circuits are configurable to form any number of (t×n/m)-bit×(t×n/m)-bit individual multipliers depending on the selected mode of operation, wherein an input to the digital signal processing region has n bits and (t×n/m) is an integer. 
     
     
       27. The programmable logic device of  claim 2  wherein the digital signal processing region is operative to generate a region output once every clock cycle of a clock signal that is input to the digital processing region. 
     
     
       28. The programmable logic device of  claim 1  wherein at least one of the multiplier circuits in the digital signal processing region comprises a plurality of smaller dedicated multiplier circuits that are configured to generate the multiplier output. 
     
     
       29. The programmable logic device of  claim 1  wherein register circuits that are used by the digital signal processing circuit are controlled by a plurality of independent sets of clear and clock signals for further control of portions of data that are registered by the register circuits and processed by the digital signal processing circuit. 
     
     
       30. The programmable logic device of  claim 1  further comprising means for dynamically or statically programming inputs to at least one of the multiplier circuits to be logically inverted. 
     
     
       31. The programmable logic device of  claim 2  wherein the digital signal processing region is configurable to perform 2n-bit×n-bit multiplication that is partly based on the addition performed by the add-subtract-accumulate circuit of two n-bit×n-bit multiplications performed by the multiplier circuits. 
     
     
       32. A programmable logic device comprising: a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
 at least one memory bit coupled to the multiplier circuit for statically controlling at least one of the two inputs to the multiplier circuit to be signed or unsigned. 
 
     
     
       33. The programmable logic device of  claim 32  wherein the at least one memory bit is stored in a memory device implemented on the programmable logic device. 
     
     
       34. A programmable logic device comprising: a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
 at least one dynamic signed/unsigned control input coupled to the multiplier circuit, wherein the at least one dynamic signed/unsigned control input recieves at least one corresponding control input signal for dynamically controlling at least one of the two inputs to the multiplier circuit to signed or unsigned. 
 
     
     
       35. A programmable logic device of comprising: a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
 at least one dynamic signed/unsigned control input coupled to the multiplier circuit, wherein the at least one register circuit for statically or dynamically controlling at least one of the two inputs to the multiplier circuit to be signed or unsigned.