Inventor

MIWA TORU

JP49 patents

⚠️ This page may combine multiple inventors who share the name “MIWA TORU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIWA TORU

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device containing bit line switches

Three-dimensional memory device containing bit line switches

Loop dependent word line ramp start time for program verify of multi-level NAND memory

Concurrent programming of multiple cells for non-volatile memory devices

Vertical resistor in 3D memory device with two-tier stack

Memory plane structure for ultra-low read latency applications in non-volatile memories

Non-volatile memory with loop dependant ramp-up rate

Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection

Concurrent programming of multiple cells for non-volatile memory devices

Differential dbus scheme for low-latency random read for NAND memories

Area effective erase voltage isolation in NAND memory

Multicore on-die memory microcontroller

Data latch programming algorithm for multi-bit-per-cell memory devices

Programming memory cells with concurrent redundant storage of data for power loss protection

Concurrent programming of multiple cells for non-volatile memory devices

Semiconductor wafer configured for single touch-down testing

Word line architecture for three dimensional NAND flash memory

SANDISK CORP

Non-volatile memory and control with improved partial page program capability

Variable program voltage increment values in non-volatile memory program operations

Systems utilizing variable program voltage increment values in non-volatile memory program operations

Circuitry and device for generating and adjusting selected word line voltage

Control gate line architecture

Non-volatile memory and control with improved partial page program capability

Program time adjustment as function of program voltage for improved programming speed in memory system

Non-volatile memory and control with improved partial page program capability

Program time adjustment as function of program voltage for improved programming speed in memory system

Program time adjustment as function of program voltage for improved programming speed in programming method

Method for generating and adjusting selected word line voltage

SANDISK TECHNOLOGIES INC

Integration of word line switches with word line contact via structures

Vertical resistor in 3D memory device with two-tier stack

Passive devices for integration with three-dimensional memory devices

Passive devices for integration with three-dimensional memory devices

Verification process for non-volatile storage

Efficient smart verify method for programming 3D non-volatile memory

Efficient smart verify method for programming 3D non-volatile memory

Verification process for non-volatile storage

Non-volatile memory with lower current program-verify

Defective word line detection

Program verify word line ramping delay for lower current consumption mode

ALROD IDAN

Non-volatile memory and methods with reading soft bits in non uniform schemes

Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling

Non-volatile memory and methods with asymmetric soft read points around hard read points

SAKAI MANABU

Write data preservation for non-volatile storage

Defective word line detection

Erratic program detection for non-volatile storage

HEMINK GERRIT JAN

Verification process for non-volatile storage

MIWA TORU

Multi-pass programming for memory with reduced data storage requirement

SONY CORP

Cathode ray tube and degaussing coil employed therein

SANDISK IL LTD

Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling