Area effective erase voltage isolation in NAND memory

Abstract

A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

What is claimed is: 
     
       1. A memory device, comprising:
 a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, the memory cell region having a plurality of non-volatile memory cells arranged in one or more arrays, and the peripheral circuitry region having at least one sense amplifier region comprised of at least one low voltage transistor; and 
 a deep N-well region formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage transistor, thereby preventing the at least one low voltage transistor from experiencing a large voltage difference between its terminals. 
 
     
     
       2. The memory device according to  claim 1 , wherein the plurality of non-volatile memory cells are three-dimensional NAND-type flash memory cells. 
     
     
       3. The memory device according to  claim 1 , further comprising at least one controller communicating with the memory cell region. 
     
     
       4. The memory device according to  claim 1 , wherein the memory cell region further comprises a plurality of three-dimensional co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate, wherein each plane is comprised of a plurality of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate. 
     
     
       5. The memory device according to  claim 4 , wherein the peripheral circuitry region further comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the plurality of sub-planes such that adjacent to each sub-plane is a sense amplifier region. 
     
     
       6. The memory device according to  claim 3 , wherein the peripheral circuitry region further comprises at least one sense amplifier driver region operatively connected to the at least one controller and the at least one sense amplifier region, and operable to provide control signals to the memory cell region, wherein the at least one sense amplifier driver region is comprised of at least one low voltage transistor. 
     
     
       7. The memory device according to  claim 6 , further comprising a voltage isolation circuit operatively connected to the sense amplifier driver region such that the at least one low voltage transistor of the sense amplifier driver region is effectively isolated from a high erase voltage (VERA) applied to the memory cell region. 
     
     
       8. The memory device according to  claim 7 , wherein the voltage isolation circuit comprises a high voltage switch transistor. 
     
     
       9. The memory device according to  claim 8 , wherein the voltage isolation circuit further comprises a sub-circuit positioned on a high voltage side of the high voltage switch transistor, the sub-circuit comprising:
 a first diode; 
 a first transistor placed in series with the first diode; 
 a second diode; and 
 a second transistor placed in series with the second diode, the sub-circuit preventing the at least one low voltage transistor of the sense amplifier driver region from experiencing a large voltage difference between terminals in the event a high erase voltage (VERA) is applied to the memory cell region. 
 
     
     
       10. A memory device, comprising:
 a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, the memory cell region having a plurality of non-volatile memory cells arranged in one or more arrays, and the peripheral circuitry region having at least one sense amplifier region and at least one sense amplifier driver region, each of the sense amplifier region and sense amplifier driver region being comprised of at least one low voltage transistor; 
 at least one controller communicating with the memory cell region, wherein the at least one sense amplifier driver region is:
 operatively connected to the at least one controller and the at least one sense amplifier region; and 
 operable to provide control signals to the memory cell region; and 
 
 a voltage isolation circuit operatively connected to the sense amplifier driver region such that, in the event a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the at least one low voltage transistor of the sense amplifier driver region is effectively isolated from the high erase voltage (VERA). 
 
     
     
       11. The memory device according to  claim 10 , wherein the voltage isolation circuit comprises a high voltage switch transistor. 
     
     
       12. The memory device according to  claim 11 , wherein the voltage isolation circuit further comprises a sub-circuit positioned on a high voltage side of the high voltage switch transistor, the sub-circuit comprising:
 a first diode; 
 a first transistor placed in series with the first diode; 
 a second diode; and 
 a second transistor placed in series with the second diode, the sub-circuit preventing the at least one low voltage transistor of the sense amplifier driver region from experiencing a large voltage difference between terminals in the event a high erase voltage (VERA) is applied to the memory cell region. 
 
     
     
       13. The memory device according to  claim 10 , wherein the plurality of non-volatile memory cells are three-dimensional NAND-type flash memory cells. 
     
     
       14. The memory device according to  claim 10 , wherein the memory cell region further comprises a plurality of three-dimensional co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate, wherein each plane is comprised of a plurality of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate. 
     
     
       15. The memory device according to  claim 14 , wherein the peripheral circuitry region comprises a plurality of sense amplifier regions arranged along the vertical axis in an alternating pattern with the plurality of sub-planes such that adjacent to each sub-plane is a sense amplifier region. 
     
     
       16. A method for effectively isolating a low voltage sense amplifier region of a non-volatile memory device from a high erase voltage (VERA) applied during a memory erase operation, comprising:
 in a memory device having a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor:
 forming a deep N-well region in the substrate; and 
 placing the memory cell region and the peripheral circuitry region on the deep N-well region such that, in the event a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage (VERA) is applied to all terminals of the at least one low voltage transistor, thereby preventing the at least one low voltage transistor from experiencing a large voltage difference between its terminals. 
 
 
     
     
       17. The method according to  claim 16 , wherein the memory cell region comprises a plurality of three-dimensional NAND-type flash memory cells. 
     
     
       18. The method according to  claim 16 , further comprising operatively connecting a voltage isolation circuit to at least one sense amplifier driver region of the periphery circuitry region, wherein the at least one sense amplifier driver region:
 is operatively connected to at least one controller of the memory device and to the at least one sense amplifier region; 
 is operable to provide control signals to the memory cell region; and 
 comprises at least one low voltage transistor. 
 
     
     
       19. The method according to  claim 18 , further comprising:
 using the voltage isolation circuit, effectively isolating the at least one low voltage transistor of the sense amplifier driver region from a high erase voltage (VERA) applied to the memory cell region. 
 
     
     
       20. The method according to  claim 19 , wherein the voltage isolation circuit comprises a high voltage switch transistor.