Inventor
BOURGEAULT MARK
CA26 patents
⚠️ This page may combine multiple inventors who share the name “BOURGEAULT MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
19 patentsUS6971083B1Nov 29, 2005
Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
ALTERA CORP70 citations95
US7676768B1Mar 9, 2010
Automatic asynchronous signal pipelining
ALTERA CORP13 citations92
US9602106B1Mar 21, 2017
Methods for optimizing circuit performance via configurable clock skews
ALTERA CORP9 citations84
US7412680B1Aug 12, 2008
Method and apparatus for performing integrated global routing and buffer insertion
ALTERA CORP16 citations84
US9584129B1Feb 28, 2017
Integrated circuit applications using partial reconfiguration
ALTERA CORP8 citations80
US10037048B1Jul 31, 2018
Methods for optimizing circuit performance via configurable clock skews
ALTERA CORP2 citations73
US10242146B2Mar 26, 2019
Method and apparatus for placing and routing partial reconfiguration modules
ALTERA CORP2 citations72
US9361421B2Jun 7, 2016
Method and apparatus for placing and routing partial reconfiguration modules
ALTERA CORP3 citations72
US7415692B1Aug 19, 2008
Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
ALTERA CORP6 citations71
US10374609B1Aug 6, 2019
Integrated circuit applications using partial reconfiguration
ALTERA CORP3 citations69
US10175734B1Jan 8, 2019
Techniques for adjusting latency of a clock signal to affect supply voltage
ALTERA CORP6 citations69
US9183336B1Nov 10, 2015
Automatic asynchronous signal pipelining
ALTERA CORP1 citations63
US11507723B2Nov 22, 2022
Method and apparatus for performing incremental compilation using structural netlist comparison
ALTERA CORP0 citations62
US11507722B2Nov 22, 2022
Method and apparatus for performing incremental compilation using structural netlist comparison
ALTERA CORP0 citations62
US11480993B2Oct 25, 2022
Methods for optimizing circuit performance via configurable clock skews
ALTERA CORP0 citations62
US10969820B2Apr 6, 2021
Methods for optimizing circuit performance via configurable clock skews
ALTERA CORP0 citations62
US8356358B2Jan 15, 2013
Preventing information leakage between components on a programmable chip in the presence of faults
ALTERA CORP3 citations62
US11381243B2Jul 5, 2022
Integrated circuit applications using partial reconfiguration
ALTERA CORP0 citations59
US8832627B1Sep 9, 2014
Automatic asynchronous signal pipelining
ALTERA CORP0 citations52