Inventor
GIRKAR MILIND
US24 patents
⚠️ This page may combine multiple inventors who share the name “GIRKAR MILIND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS11200055B2Dec 14, 2021
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP14 citations94
US10785028B2Sep 22, 2020
Protection of keys and sensitive data from attack within microprocessor architecture
INTEL CORP16 citations94
US8037465B2Oct 11, 2011
Thread-data affinity optimization using compiler
INTEL CORP28 citations92
US7657880B2Feb 2, 2010
Safe store for speculative helper threads
INTEL CORP26 citations92
US7487502B2Feb 3, 2009
Programmable event driven yield mechanism which may activate other threads
INTEL CORP19 citations92
US7398521B2Jul 8, 2008
Methods and apparatuses for thread management of multi-threading
INTEL CORP26 citations92
US7020873B2Mar 28, 2006
Apparatus and method for vectorization of detected saturation and clipping operations in serial code loops of a source program
INTEL CORP33 citations92
US6367070B1Apr 2, 2002
Means and method for establishing loop-level parallelism
INTEL CORP39 citations92
US6272676B1Aug 7, 2001
Method and apparatus for finding loop— lever parallelism in a pointer based application
INTEL CORP36 citations92
US7571301B2Aug 4, 2009
Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors
INTEL CORP23 citations90
US7328433B2Feb 5, 2008
Methods and apparatus for reducing memory latency in a software application
INTEL CORP19 citations90
US11023231B2Jun 1, 2021
Systems and methods for executing a fused multiply-add instruction for complex numbers
INTEL CORP8 citations84
US7603546B2Oct 13, 2009
System, method and apparatus for dependency chain processing
INTEL CORP10 citations81
US12260213B2Mar 25, 2025
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP1 citations75
US12124847B2Oct 22, 2024
Systems, methods, and apparatuses for tile transpose
INTEL CORP0 citations73
US11838418B2Dec 5, 2023
Protection of keys and sensitive data from attack within microprocessor architecture
INTEL CORP3 citations73
US11036499B2Jun 15, 2021
Systems, apparatuses, and methods for controllable sine and/or cosine operations
INTEL CORP2 citations73
US10877910B2Dec 29, 2020
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations72
US10459858B2Oct 29, 2019
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations72
US11579871B2Feb 14, 2023
Systems, apparatuses, and methods for controllable sine and/or cosine operations
INTEL CORP0 citations62
US9910796B2Mar 6, 2018
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations62